JPH0224017B2 - - Google Patents

Info

Publication number
JPH0224017B2
JPH0224017B2 JP56101896A JP10189681A JPH0224017B2 JP H0224017 B2 JPH0224017 B2 JP H0224017B2 JP 56101896 A JP56101896 A JP 56101896A JP 10189681 A JP10189681 A JP 10189681A JP H0224017 B2 JPH0224017 B2 JP H0224017B2
Authority
JP
Japan
Prior art keywords
layer
patterned
mask
etching
intermediate layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56101896A
Other languages
English (en)
Japanese (ja)
Other versions
JPS583232A (ja
Inventor
Moritaka Nakamura
Toshihiko Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10189681A priority Critical patent/JPS583232A/ja
Publication of JPS583232A publication Critical patent/JPS583232A/ja
Publication of JPH0224017B2 publication Critical patent/JPH0224017B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
JP10189681A 1981-06-30 1981-06-30 パタ−ン形成方法 Granted JPS583232A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10189681A JPS583232A (ja) 1981-06-30 1981-06-30 パタ−ン形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10189681A JPS583232A (ja) 1981-06-30 1981-06-30 パタ−ン形成方法

Publications (2)

Publication Number Publication Date
JPS583232A JPS583232A (ja) 1983-01-10
JPH0224017B2 true JPH0224017B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-05-28

Family

ID=14312677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10189681A Granted JPS583232A (ja) 1981-06-30 1981-06-30 パタ−ン形成方法

Country Status (1)

Country Link
JP (1) JPS583232A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60167428A (ja) * 1984-02-10 1985-08-30 Mitsubishi Electric Corp 微細加工方法
JPH0626203B2 (ja) * 1984-11-19 1994-04-06 三菱電機株式会社 微細加工方法
DE3879186D1 (de) * 1988-04-19 1993-04-15 Ibm Verfahren zur herstellung von integrierten halbleiterstrukturen welche feldeffekttransistoren mit kanallaengen im submikrometerbereich enthalten.

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5851412B2 (ja) * 1975-03-19 1983-11-16 株式会社日立製作所 半導体装置の微細加工方法
JPS55151338A (en) * 1979-05-16 1980-11-25 Matsushita Electric Ind Co Ltd Fabricating method of semiconductor device

Also Published As

Publication number Publication date
JPS583232A (ja) 1983-01-10

Similar Documents

Publication Publication Date Title
US4132586A (en) Selective dry etching of substrates
Lin et al. Practicing the Novolac deep‐UV portable conformable masking technique
JPH035573B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP2639372B2 (ja) 半導体装置の製造方法
JPH0224017B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
US5064748A (en) Method for anisotropically hardening a protective coating for integrated circuit manufacture
US6372414B1 (en) Lift-off process for patterning fine metal lines
JPH0466345B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH08272107A (ja) レジストパターンの形成方法
JPH05109673A (ja) 半導体装置の製造方法
JPH02156244A (ja) パターン形成方法
JPH0434815B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH05142788A (ja) レジストパターンの形成方法
JP2521329B2 (ja) 半導体装置の製造方法
JPH0319696B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS5937494B2 (ja) 薄膜のパタ−ン形成法
CN120712527A (zh) 作为薄car的底层以改良图案转移的euv敏感金属氧化物材料
JPH06349728A (ja) レジストパターンの形成方法
JP2000323452A (ja) ドライエッチング方法
JPS646448B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP2930604B2 (ja) レジストパターンの形成方法
JPH05303210A (ja) パターン形成方法
JP2001148562A (ja) 配線基板の製造方法
JPH03188447A (ja) レジストパターンの形成方法
JPH03159127A (ja) 半導体装置の製造方法