JPH02189934A - Manufacture of thin-film transistor - Google Patents

Abstract

PURPOSE:To form a gate electrode and source-drain regions in a self-alignment manner by shaping a poly-Si layer, to which an impurity is doped previously in high concentration, forming a poly-Si film, an inter-layer insulating film and a poly-Si layer for the gate electrode onto the poly-Si layer layer and implanting the ions of the impurity. CONSTITUTION:A poly-Si layer 2 is doped with an impurity in high concentration through a thermal diffusion method. A poly-Si film 3 is formed onto the layer 2 through a vacuum CVD method, and a gate insulating film 4 is shaped through thermal oxidation. Since the impurity is diffused into the undoped poly-Si film 3 as an upper layer from the high-concentration impurity doped poly-Si layer 2 at the same time, poly-Si layers 3' which is doped with the impurity in high concentration are also formed as a whole in source-drain region corresponding sections. A poly-Si layer 6 for a gate electrode is shaped onto the gate insulating film 4, and impurity ions are implanted 5 from the upper section of the layer 6. Accordingly, source-drain regions 7 which is doped with the impurity in high concentration are formed together with the gate electrode 6 which is doped with the impurity in low concentration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an MO8 thin film transistor useful as a drive circuit for image sensors, displays, etc.

[Prior art]

In MO8 type thin film transistors (hereinafter referred to as TPT) that use non-single crystal Si such as poly-Si for the active layer, the channel region is thinned to increase the on/off current ratio in the channel region, and on the other hand, the metal wiring In order to lower the contact resistance and the source/drain resistance, the source/drain regions are made thicker or doped with impurities. In fact, for example, in JP-A-61-48975 and JP-A-61-48976, the channel region is made thinner than the source/drain region by selective etching, and in JP-A-59-205761, the channel region is similarly made thinner than the source/drain region by selective thermal oxidation. It is made thinner than the drain region, and impurities are doped into the source/drain region from the contact hole by a thermal diffusion method in Japanese Patent Laid-Open No. 59-132168.

In the conventional method described above, the source and
The portion corresponding to the drain region is not doped with impurities. Therefore, it is necessary to dope the portion with impurities at a high concentration in a subsequent step. Conventionally, the following three methods have been used as impurity doping methods in this case.

1) All impurities are doped by ion implantation.

2) All impurities are doped by thermal diffusion.

3) After doping a small amount of impurity by ion implantation, the impurity is thermally diffused into the contact portion.

However, since method 1) all uses ion implantation, the varnish l-
Becomes high. In method 2), it is difficult to ensure reliability due to problems such as leakage current from the electrode to the source/drain region. Furthermore, when controlling the film thickness by selective etching or selective thermal oxidation, there is a problem in the flexibility and controllability of the thickness of the source/drain region and the channel region.

(In this method, the thickness of the channel region is determined by the thickness of the thermal oxide film. For example, if the thickness of the thermal oxide film is 1000, the channel region will be approximately 5 mm thick compared to the source/drain region.
Only 00 people become thinner. ) Also, method 3) is not suitable for devices with short channel lengths because the implanted impurities re-diffuse during subsequent thermal diffusion. The resistance of the source/drain regions may also be a problem.

[Problem to be solved by the invention]

The object of the present invention is to have low cost and high reliability, be applicable to short channel lengths, expand the degree of freedom in controlling the thickness of the source/drain region and the channel region, and It is an object of the present invention to provide a method for manufacturing an MO8 type thin film 1-run sister which can stably reduce the resistance of the region.

[Structure and operation of the invention]

The manufacturing method of the thin film 1 helangister of the present invention is based on ``insulating substrate''.
After forming a poly-Si layer doped with impurities at a high concentration in advance in the parts corresponding to the second source and first rain regions, a poQ and y-Si film is formed on it, and an interlayer insulating film is formed on it by thermal oxidation. , and then a gate electrode po
ly-5j layer is formed, and then the gate electrode and the source electrode are formed in a self-aligned manner by impurity ion implantation.
The method is characterized in that it includes a step of forming a drain region.

An example of the method of the present invention will be explained with reference to FIG. 1. First, a poly-5J film that will become part of the active layer is formed on an insulating substrate 1 such as a glass plate by low pressure CVD, and then a poly-5J film that will become a part of the active layer is formed. Remove by etching leaving only a portion. Next, a high concentration of impurities (P or As in the case of N-channel TPT fabrication) is added into this poly-8i layer by thermal diffusion.
, B) for P-channel TPT fabrication (
Figure 1(a)). Note that 2 is a poly-5J layer doped with impurities at a high concentration (approximately 10"/cm3). Next, a poly-5J film 3 is formed on it by low pressure CVD (Fig. 1(b)). .Next, thermal oxidation is performed to form a gate insulating film 4 (Fig. 1C).

At this time, high concentration impurity doped poly-SiJ?
Since the impurity diffuses from iJ2 into the upper non-doped poly-Si film 3, the portion corresponding to the source/drain region has a high concentration as a whole (the concentration is on the same order as that of the po12y-3j layer 2, or for example, 1/2 of that). A pony-Si layer 3' doped with impurities to a certain degree is also formed. Next, poly-Si was deposited on the gate insulating film 4 by low pressure CVD method.
After forming a film and etching it to a desired size to form Goo 1 to poly-Si layer for electrodes, impurity ion implantation 5 is performed from above to form Goo 1 to poly-Si for electrodes in a self-aligned manner.
Impurities are doped in the ly-si layer and in the highly impurity-doped poQ and y-81 layers 3' via the gate insulating film 4. As a result, the gate electrode 6 doped with impurities at a low concentration
At the same time, source/drain regions 7 doped with impurities at a high concentration (however, a portion 8 in contact with the channel region 9 is doped with a low concentration of impurities) are formed (FIG. 1(d)). In this case, the dose of impurities may be 1/10 to 1/100 of the usual dose. Hereafter, SiO
□, PSG (phosphorus glass), BSG (borate glass)
After forming an interlayer insulating film 10 and opening a contact hole, a metal (usually i) wiring 11 is formed in this contact area (FIG. 1(e)), and finally hydrogen treatment (poly-
The TPT of the present invention can be obtained by performing an operation for removing defects at Si grain boundaries.

As mentioned above, in a TPT, the thickness of the channel region must be as thin as possible (approximately 500 Å or less) in order to improve transistor characteristics, and the thickness of the source/drain regions must be increased.

In this example, the thickness of the channel region was 500 mm, and the thickness of the source/drain regions was 1000 mm.

Note that the thickness of the thermal oxide film (gate insulating film) is 800 mm. The channel length was shortened to 5 μm (channel width was 40 μm). Also, the impurity dose by ion implantation method is L
O14/d (1/10 to 1/100 of normal), but as mentioned above, pony-Si doped in advance at a high concentration was used.
Since the layer was formed in advance, the resistance of the source/drain region near the contact could be made as low as about 10<-3 >[Omega]. At this time, the transistor characteristics will be as shown in Figure 2,
All impurity doping is done by ion implantation at a dose of 101G.
There was no inferiority compared to the comparative amount (Fig. 3) conducted with /d. Note that both cases are for N-MO8 type TPT.

[Function and effect of the invention]

Since the method of the present invention does not require all impurity doping by ion implantation or thermal diffusion, it is lower in cost than a method in which all impurities are doped by ion implantation, and is more reliable than a method in which all impurities are doped by thermal diffusion. In addition, compared to the method of doping impurities by ion implantation and then thermally diffusing the impurities into the contact area, it can be applied to devices with short channel lengths and can stably lower the resistance of the source/drain regions. . Furthermore, regarding the control of the thickness of the source/drain region and the channel region, it has advantages such as higher reliability than the method using selective etching, and a greater degree of freedom than the method using selective oxidation.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are process diagrams for manufacturing a TPT according to the method of the present invention, and FIGS. 2 and 3 show transistor characteristics of an example of TPT manufactured using the method of the present invention and the conventional method, respectively. 1... Insulating substrate 2... Highly doped poly-Si layer 3
...Poly-Si film 3'...Poly-Si layer doped with impurities at high concentration 4...Gate insulating film 5...Impurity ion implantation 6
...po12y-Si layer 7 for gate electrode...source/drain region 8...low concentration impurity doped portion 9...channel region 10...interlayer insulating film 11...
...Metal wiring patent applicant Ricoh Co., Ltd. and one other representative Patent attorney Sa 1) Moriyu and one other person - Gate voltage Vg (V) Figure 3 = 8 Gate voltage VCI (V”)

Claims (1)

[Claims] 1. After forming a poly-Si layer doped with impurities at a high concentration in advance in a portion corresponding to the source/drain region on an insulating substrate, a poly-Si film is formed on the poly-Si layer, and then a poly-Si film is formed on the poly-Si layer. A process of forming an interlayer insulating film by thermal oxidation, forming a poly-Si layer for a gate electrode on top of it, and then forming a source/drain region along with the gate electrode in a self-aligned manner by implanting impurity ions from above. A method for manufacturing a thin film transistor, comprising: