JPH02188945A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an interlayer insulating film whose surface is flat without a steep recessed part or the like on a wiring-part formation face including wiring parts ar ranged at very small intervals and which has no cavity part built-in by a method wherein a plurality of kinds of liquid-phase insulating films with different viscosities are coated one after another in the order of a lowest-viscosity film onward and are solidified. CONSTITUTION:When the surface of a substrate having a plurality of groove parts 4A, 4B whose opening width (w) is different is coated with a liquid-phase insulating film, a plurality of kinds of liquid-phase insulating films 105, 106 with different viscosities are coated one after another in the order of a lowest-viscosity film onward and are solidified. For example, a first vapor-growth insulating film 3 of SiO2, PSG or the like is formed on a substrate on which lower-layer Al wiring parts 2A to 2C have been formed on a lower-layer insulating film 1 at a narrow interval d1 and at a wide interval d2. Then, said substrate is coated with a first low-viscosity liquid- phase insulating film 105 by a spin coating method; and this assembly is cured in N2 at a temperature of about 250 to 300 deg.C for about 30 minutes to form a first silicon oxide film 5. Then, a second high-viscosity liquid-phase insulating film 106 is coated by the spin coating method; and a second silicon oxide film 6 is formed in the same manner as the above-mentioned film.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, particularly a method for flattening a surface on which upper layer wiring is formed in a semiconductor device with a multilayer wiring structure, the present invention relates to a method for manufacturing a semiconductor device, in particular a method for flattening a surface on which upper layer wiring is formed in a semiconductor device having a multilayer wiring structure. With the aim of forming an interlayer insulating film with a flat surface without steep recesses and no built-in cavities, multiple types of liquid phase insulating films with different viscosities are sequentially applied, starting with the one with the lowest viscosity. The method includes a step of coating and solidifying, or on a base surface on which a plurality of wiring patterns are disposed on an underlying insulating film through gaps of different widths, the gaps between the wiring patterns are formed along the inner surface of the substrate surface. depositing a first vapor-grown insulating film on the substrate to a thickness that covers the substrate;
a step of applying and curing a liquid phase insulating film, and a second liquid phase having a higher viscosity than the first liquid phase insulating film flowing only into the gap having a wide opening width and filling the gap on the substrate; A step of applying and curing the insulating film, and exposing the solidified second liquid phase insulating film and first liquid phase insulating film to the upper surface of the first vapor grown insulating film on the lower wiring pattern. and a step of depositing a second vapor-phase insulating film on the finished surface of the etching pack.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for flattening a surface on which upper layer wiring is formed in a semiconductor device having a multilayer wiring structure.

2. Description of the Related Art In large-scale, highly integrated semiconductor devices such as LSIs, circuit configurations are often made of internal wiring having a multilayer wiring structure.

In a multilayer wiring structure in which a plurality of wiring layers are laminated with interlayer insulation films interposed therebetween, the irregularities that occur on the interlayer insulation film that is deposited on the wiring formation surface are added up sequentially from the lower layer and increase as the layer increases toward the upper layer. It is said that uneven steps are formed, and this high step difference causes step breakage in the wiring formed on the interlayer insulating film or a similar deterioration in the quality of the wiring, which reduces the manufacturing yield and reliability of semiconductor devices. There's a problem.

Therefore, in a semiconductor device having a multilayer wiring structure, it is an important issue to planarize the surface of the interlayer insulating film, that is, the surface on which the wiring is formed.

[Conventional technology]

Recently, when manufacturing semiconductor devices with multilayer wiring structure, many technologies have been used to planarize the wiring formation surface.
Spin-on glass (S,
0. G), a spin-coded layer of a liquid phase insulating film made of organic resin such as polyimide, and silicon dioxide (SiO
Vapor phase growth (CVD) such as □) and phosphosilicate glass (PSG)
There is a planarization technology that uses a combination with an insulating film.

A method for forming multilayer wiring using the conventional planarization technique is as follows.

That is, as shown in FIG. 4(a), a plurality of lower layer wiring patterns 52A, 52B, 52C, etc. are formed on a lower layer insulating film 51 with different wiring spacings, that is, different wiring gap aspect ratios, on a base body. First, a first CVD insulating film 53 having a thickness of about 1 to 172 times the height of the wiring is deposited. Here, due to the poor step coverage of the insulating film formed by vapor phase growth, the surface of the first 07-hole insulating film 53 has gaps on the lower wiring patterns 52A, 52B, 52C, etc. that correspond to the steps of these wirings. Groove portions 54A, 54B, etc., having a depth and a steep step difference and having different widths and shapes are formed.

Next, as shown in FIG. 4(5), the first CVD insulation If! A groove 52B having a wide width is formed on the attachment surface of 53.
One type of liquid phase insulating film, for example, S, 0. A G layer 55 is formed by coating by a spin code method, and is coated with S, 0. The G layer 55 is cured and solidified. At this time, since S, 0.0 has a high viscosity, S, O, and C do not flow into the groove 54A having an extremely narrow opening width, and a cavity 56 remains in the groove 54A.

Next, as shown in FIG. 4(C), S, O, and C are removed by reactive ion etching (RIB), which is an etching method that has anisotropy predominant in the direction perpendicular to the substrate surface.
The layer 55 and the CVD insulating film 53 below it are deposited on top of the lower wiring patterns 52A, 52B, 52C, etc.
.

Etch back to the extent that the first CVD insulating film 53 having a thickness of approximately 2,000 mm is left.

Here, the groove portion 54A, which has an extremely narrow opening width and does not contain the S, O, and C layers, is opened again and exposed.

Next, as shown in FIG. 4(d), a second CVD insulator M51 of a required thickness, which is the remaining part of the interlayer insulating film, is formed on the etched back substrate.

At this time, the groove portion 54^ having the narrow opening width remains as a cavity portion 58 again, and the second CV on this cavity portion 58
A first wedge-shaped recess 59 corresponding to the opening of the groove 54B is formed on the surface of the D insulating film 57.

Next, as shown in FIG. 4(e), the second CVD
A wiring metal layer is formed on the insulating film 57 by sputtering, and patterning is performed by ordinary photolithography to form an upper wiring pattern 60.

[Problem to be Solved by the Invention] However, according to the above conventional method, as shown in FIG. 2(d), the first CVD insulating film 53 and the second CVD insulating film 57 forming the interlayer insulating film are , for example, lower layer wiring pattern 5
By incorporating the cavity 58 in a narrow gap such as between 2A and 52B, the insulation properties of the interlayer insulating film are reduced.

In addition, a second CVD film is formed on the surface where the upper layer wiring pattern 60 is formed.
Since the first wedge-shaped recess 59 is formed on the surface of the insulating film 57 at a position above the location where the cavity 58 is formed,
A deep second wedge-shaped recess 61 corresponding to the first wedge-shaped recess 59 is formed on the upper layer wiring pattern 60 formed by a method with poor step coverage such as sputtering, and the cross-sectional area of the wiring at that portion is formed. There is a problem in that wire breakage due to electromigration or stress migration is more likely to occur.

Therefore, the present invention aims to form an interlayer insulating film having a flat surface without steep recesses, etc., and having no built-in cavities on a wiring formation surface including wiring arranged at minute wiring intervals. purpose.

[Means to solve the problem]

The above problem is that when flattening the upper surface of a substrate having multiple grooves with different opening widths by applying a liquid-phase insulating film, it is necessary to apply multiple types of liquid-phase insulating films with different viscosities in order from the lowest to the lowest. A method for manufacturing a semiconductor device according to the present invention including a step of solidifying a plurality of lower N&! When forming an interlayer insulating film with a flat surface on a substrate surface in which line patterns are disposed through gaps of different widths, on the substrate surface, the gaps of the lower wiring pattern are formed on the inner surface of the substrate surface. depositing a first vapor-deposited insulating film to a thickness that covers the first
A step of applying a first liquid phase insulating film having a viscosity low enough to flow into and fill the narrow gap on the substrate on which the vapor grown insulating film is deposited, and curing and solidifying the first liquid phase insulating film.
On the substrate on which the solidified layer of the first liquid phase insulating film is deposited, the first liquid insulating film flows into only the wide gap and fills the wide gap.
A process of applying and curing a second liquid phase insulating film having a higher viscosity than that of the liquid phase insulating film, and anisotropic drying of the solidified second liquid phase insulating film and the first liquid phase insulating film. a step of etching back until the upper surface of the first vapor-grown insulating film on the lower wiring pattern is exposed by an etching means; and depositing a second vapor-growing insulating film on the etched-back surface. The problem is solved by a method for manufacturing a semiconductor device according to the present invention, which includes a step of:

[For production]

When a liquid-phase insulating film is applied onto a substrate by a normal spin-coating method, the low-viscosity liquid-phase insulating film easily flows into narrow grooves, fills them, and remains; In this case, the coating is applied only along the inner surface and filling in the sharp corners, and multiple coatings are required to fill the entire wide groove. In addition, a high-viscosity liquid-phase insulating film does not flow into a narrow groove, but instead covers it and leaves a cavity in the groove, but it easily flows into a wide groove. It has the property of filling the groove almost completely with one application.

Therefore, the present invention has been developed to provide a surface of a first vapor phase grown insulating film which is a negative part of an interlayer insulating film deposited on a lower layer wiring forming surface on which wirings are formed at different intervals. A low-viscosity liquid-phase insulating film is coated with a spin cord or the like on the correspondingly formed first groove with a narrow width and a large aspect ratio, and on the sharp corners of the wide groove with a small aspect ratio and cured. After filling the wide grooves that cannot be filled with the low-viscosity liquid-phase insulating film, a high-viscosity liquid-phase insulating film is preferably applied once using a spin cord or the like. Fill completely with cure.

As a result, the surface etched back so as to leave the solidified liquid-phase insulating film only in the groove becomes an excellent flat surface free of wedge-shaped recesses caused by the cavities between the lower wirings. Therefore, the surface of the second vapor-phase insulating film deposited as the remainder of the interlayer insulating film on this surface also becomes an excellent flat surface with no wedge-shaped recesses, thereby preventing defects in the upper layer wiring formed thereon. This guarantees its authenticity.

Further, as described above, since there is no cavity in the interlayer insulating film, high insulation between wirings is ensured.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

Figure 1 is a process cross-sectional view of an embodiment of the method of the present invention, Figure 2 is a molecular structure diagram of 0CD type 2, which is an example of low-viscosity spin-on glass (S, O, G), and Figure 3 is a high-viscosity spin-on glass (S, O, G). S, 0. FIG. 1 is a molecular structure diagram of 0CDt, 1, which is an example of G.

Refer to FIG. 1(a) When forming a multilayer wiring structure of a semiconductor device by the method of the present invention, for example, 0.5 to 0.0.
The lower layer aluminum (with a width of 1 μm and a height of about 1 μm) is formed with a narrow interval d of approximately 6 μm and a wide interval d2 of approximately 1 to 2 am.
AI) First, on the substrate on which the wirings 2A, 2B, and 2C are formed, it has the function of suppressing old protrusions during heat treatment and preventing leakage between wirings via the surface of the lower layer insulation film 1, and Thickness of part is about 0.1~0.2 pm 5i
A first vapor phase growth insulating film 3 of Oz, PSG, etc. is formed.

Here, the first groove 4A having a narrow opening width W of about 0.1 to 0.2 μm and a large aspect ratio is formed in the narrow wiring spacing portion, and the first groove 4A having a large aspect ratio is formed in the wide wiring spacing portion. 8
A second groove 4B having a wide opening width 2 on the order of μm and a small aspect ratio is formed.

Refer to FIG. 1(b) Next, a low-viscosity first liquid-phase insulating film 105 is coated on the substrate by a conventional spin coating method.

The first liquid phase insulating film 105 having a low viscosity has a molecular structure as shown in FIG. 2, for example, and a viscosity of 0.5 to 2.
．． Oc, S of about p, 0. 0CD type-z (
(manufactured by Tokyo Ohka). Note that an alcohol solvent is used to adjust the viscosity.

Due to this spin code, the first groove 48 with a large aspect ratio and narrow opening width 1 is filled with 0CDiyp, □ without any gaps, and the upper surface of the first vapor grown insulating film 3 and the opening width -2 A first liquid-phase insulating film 105 is deposited on the inner surface of the second groove 4B having a small aspect ratio of 0.1 μm or less, and on the sharp corner 4BB at the bottom of the second groove 4B. The first vapor phase growth insulating film 3 is deposited to a thickness of about 0.2 to 0.3 μm.

Referring to FIG. 1(C), the above substrate was then placed in nitrogen (N2) at 250 to 3
The first liquid phase insulating film 105 is cured by heating at a temperature of about 00° C. for about 30 minutes. Due to this curing, the 0CDcyp=z is dehydrated and condensed to form the first silicon oxide (SiO+5iOz) film 5.

Referring to FIG. 1(d), a high viscosity liquid phase insulating film 106 is then coated on the substrate by a conventional spin coating method. The second liquid phase insulating film 106 having a high viscosity has a molecular structure as shown in FIG. 3, and has a viscosity of 2.0 to 5.0, c,
S of about p, 0. G, 0CD type, t (manufactured by Tokyo Ohka) is used. Note that an alcohol solvent is used to adjust the viscosity.

Due to this spin code, the second groove 4A having the wide opening width -2 and having a small aspect ratio is filled with the OCDty-w, which is the second liquid phase insulating film 106, without any gaps, and the upper part of the base body has a thickness of 0. A second liquid phase insulating film 106 having a thickness of about 5 to 1 μm is formed.

Refer to FIG. 1(e). Next, the above substrate is heated in N2 at a temperature of about 250 to 300"C for about 30 minutes to cure the second liquid phase insulating film 106, which is then subjected to a second oxidation process by dehydration condensation. silicon(
The film is changed into a SiO+SiO□) film 6.

Refer to FIG. 1(f). Next, the second silicon oxide film 6 and the first silicon oxide film 5 are etched into the first silicon oxide film on the lower wiring pattern by a reactive ion etching (RIE) process using, for example, methane trifluoride. Etch back is performed until the upper surface of the vapor grown insulating film 3 is exposed. On this etchback surface, since the inside of the narrow first groove 4^ formed in the narrow interconnect interval is completely filled with the first silicon oxide film 5, a wedge-shaped portion is also formed on the upper surface of this portion. No recesses are formed, resulting in an excellent flat surface with no irregularities.

Next, on the etched back surface, a second vapor phase growth insulating film 7 made of SiO□ or PSG with a thickness of about 0.6 μm, which is the remaining part of the interlayer insulating film, is formed. The vapor-phase grown insulating film 7 also becomes an excellent flat surface with no unevenness, following the etched back surface.

Refer to FIG. 1(c) Next, the film is composed of the first vapor grown insulating film 3, the first silicon oxide film 5, the second silicon oxide film 6, and the second vapor grown insulating film 7 on the surface layer. An A1 layer with a thickness of about 1 μm, for example, is formed by sputtering as a wiring material layer on the interlayer insulating film, and patterned by ordinary photolithography to form a wiring material layer of, for example, 2 μm in width and 1 μm in thickness.
After forming the upper layer AI wiring 8 of about m, the multilayer wiring structure according to the present invention is completed. As mentioned above, since the surface of the second vapor-phase grown insulating film 7, which is the wiring formation surface, is formed as an excellent flat surface with no unevenness, it is possible to No deformation occurs and high reliability of the wiring is ensured.

In the above example, the spin code curing process of the first liquid phase insulating film and the spin code curing process of the second liquid phase insulating film were performed only once, but the filling was insufficient. In this case, it is desirable to repeat the above steps multiple times.

Furthermore, although S, O, and C1 are used as the liquid phase insulating film, they are not limited to S, O, and G, and heat-resistant organic insulating films such as polyimide may also be used.

Furthermore, three or more types of liquid phase insulating films having different viscosities may be used, and the spin code curing process may be performed three or more times.

Note that the coating method is not limited to the spin code method.

〔Effect of the invention〕

As described above, according to the present invention, deformation that would reduce the cross-sectional area of the upper layer wiring in a multilayer wiring structure is prevented, so that reliability of the wiring is improved.

Therefore, the present invention can be applied to large-scale devices such as LSIs with multilayer wiring.
This is effective in improving the reliability of highly integrated semiconductor devices.

Cross-sectional view, FIG. 2 shows S,0. 0CD, which is an example of G
Molecular structure diagram of type*t. Figure 3 is 0CD, which is an example of S, O, and G with high viscosity.
Type? Figures 4(a) to 4(e) are cross-sectional views of the conventional method.

In the figure, l is the lower insulating film, 2^, 2B, 2C are lower layer AI wiring, 3 is a first vapor phase growth insulating film; 4A is a first groove with a narrow opening width; 4B is a second groove with a wide opening width; 48B is a sharp corner, 5 is a first silicon oxide film;

[Brief explanation of the drawing]

In FIGS. 1A to 1C, Step 8 of an embodiment of the method of the present invention shows an upper layer AI wiring, 105 shows a first liquid phase insulating film, and 105 shows a second liquid phase insulating film. Kimata illumination 5th n-jitsugoi 1n construction tI town map No. I
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Claims (2)

[Claims] (1) When flattening the upper surface of a substrate that has multiple grooves with different opening widths by applying a liquid-phase insulating film, multiple types of liquid-phase insulating films with different viscosities are sequentially applied and solidified, starting from the lowest viscosity. 1. A method of manufacturing a semiconductor device, the method comprising the step of: (2) When forming an interlayer insulating film with a flattened surface on a base surface in which a plurality of lower layer wiring patterns are disposed on the lower layer insulating film through gaps of different widths, the base surface depositing a first vapor grown insulating film on top of the lower wiring pattern to a thickness that covers the gap portion of the lower wiring pattern along the inner surface thereof; a step of applying a first liquid insulating film having a viscosity low enough to flow into and fill the narrow gap on the substrate and curing and solidifying the solidified layer of the first liquid insulating film; A step of applying a second liquid phase insulating film having a higher viscosity than the first liquid phase insulating film to the extent that it flows only into the gap having a wide opening width and filling it on the adhered substrate, and curing and solidifying the second liquid phase insulating film. , Etching the solidified second liquid phase insulating film and first liquid phase insulating film by anisotropic dry etching until the upper surface of the first vapor grown insulating film on the lower wiring pattern is exposed. 1. A method of manufacturing a semiconductor device, comprising the steps of etching back, and depositing a second vapor-phase insulating film on the etched back surface.