JPH0786284A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To flatten a layer insulating film in a semiconductor device of a multilayer interconnection structure, and to prevent the generation of surface grooves and cracks in the layer insulating film. CONSTITUTION:A first wiring layer 13 is formed on the insulating film 12 a semiconductor substrate 11, and on this a first layer insulating film 14 is formed. On it an SOG layer 15 is applied to a film thickness equal to 1/5-1/3 of that of the first wiring layer 13, and the level difference among the first wiring layer 13 is lessened. And on it a second layer insulating film 16 is formed so as to be thicker than the first wiring layer 13. Then the surface of the second layer insulating film 16 is flattened by chemical mechanical grinding, and on it a second wiring layer 18 is formed. It becomes possible to prevent the generation of of 'blowholes' and to make flatness and reliability higher, by providing the SOG layer 15 as a lower layer to the second layer insulating film 16. Besides, it becomes possible to prevent the generation of cracks and to raise the reliability of the layer insulating film by forming the SOG layer 15 thinly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring structure, and more particularly to a semiconductor device having an interlayer insulating film whose wiring structure is flattened and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices have been highly integrated, wiring layers have become multi-layered, and a difference in height between a region where wiring exists and other regions inside the semiconductor device has occurred. The step difference due to the difference in height between the overlapping area and the other area is extremely remarkable. Due to this step, there is a problem that disconnection due to step breakage easily occurs in the wiring layer formed on the upper side of the interlayer insulating film. Therefore, attempts have been made to flatten the interlayer insulating film. As one of them, embedding the unevenness of the lower wiring layer with an insulating material,
There is a technique to mitigate the step at that portion. Japanese Patent Laid-Open No. 2-12
The one disclosed in Japanese Patent No. 2654 is an example thereof. That is, as shown in FIG. 5A, after the first metal wiring 33 is formed on the semiconductor substrate 31 through the insulating film 32, the CVD method (chemical vapor deposition) is performed on the first metal wiring 33. The first interlayer insulating film 34 is formed by using the phase growth method), and the SOG (spin on glass) layer 35 is further applied thereon to form the first interlayer insulating film 34.
The recesses between the metal wirings 33 are almost filled.

Next, as shown in FIG. 5B, the SOG layer 3
A second interlayer insulating film 36 is formed on the film 5 by a CVD method so as to have a predetermined film thickness. Then, as shown in FIG. 5C, a through hole 37 is formed at a required position of the first and second interlayer insulating films 34 and 36, and a second metal wiring is formed on the second interlayer insulating film. 38 is formed. As described above, the narrow portion between the first metal wirings 33 is embedded by using the SOG layer 35 to mitigate the step difference on the surface, flatten the surface of the second interlayer insulating film 33, and It is possible to prevent disconnection in the wiring 38.

However, according to this technique, when the SOG layer 35 is applied, the SOG layer 35 is applied thickly in a narrow portion between the first metal wirings 33 and thinly applied in a wide portion between the first metal wirings 33. Since it is easy, the surface of the second interlayer insulating film 36 formed thereon is likely to have gradual unevenness along with it. Therefore, the first and second metal wirings 33, 3
A large difference occurs in the surface height between the region where 8 is overlapped and the region where no metal wiring is present, and as a result, the focus margin (allowable depth of focus) in the photolithography process in the subsequent process. There was a problem that was smaller. In order to solve this problem, SO
Although it is sufficient to apply the G layer 35 sufficiently thickly, the SOG layer is mechanically weak and easily cracked, so that the reliability of the SOG layer is deteriorated and the reliability of the wiring formed thereon is also deteriorated. As a result, the reliability of the completed semiconductor device is reduced.

Therefore, as another conventional flattening technique, S
A technique for forming a flat surface of an interlayer insulating film without using an OG layer has been developed. For example, Japanese Patent Laid-Open No. 2-177
In the technique disclosed in Japanese Patent Publication No. 433, a first metal wiring 43 is formed on a semiconductor substrate 41 via an insulating film 42 and then formed on the first metal wiring 43 as shown in FIG. The interlayer insulating film 44 is formed sufficiently thick by using the CVD method so that the metal wiring is completely buried. Then, Fig. 6
As shown in (b), the interlayer insulating film 44 is surface-polished and flattened by the CMP method (chemical mechanical polishing method). Then, as shown in FIG. 6C, a through hole 45 is opened at a required portion of the interlayer insulating film 44, and a second metal wiring 46 is formed.

[0006]

In the latter CMP method, the entire surface of the semiconductor device can be globally planarized, but the interlayer insulating film 44 needs to be formed sufficiently thick. As shown, "X" X is generated in this insulating film in the portion where the interval between the first metal wirings 43 is narrow, and CM
After the surface of the inter-layer insulation film 44 is polished by the P method, the recessed groove X'may be formed due to this "su". When such a groove X'is formed, polishing debris and a polishing agent for the insulating film, which are generated during CMP, are accumulated in the groove X ', which causes deterioration of the characteristics and reliability of the semiconductor device. There's a problem. An object of the present invention is to provide a highly reliable semiconductor device which is free from cracks and surface recesses and which is flattened to prevent disconnection of an upper layer wiring, and a manufacturing method thereof.

[0007]

The semiconductor device of the present invention comprises:
A first wiring layer and a first wiring layer formed on the first wiring layer
Interlayer insulating film, an SOG layer formed on the first interlayer insulating film, a second interlayer insulating film formed on the SOG layer and having a flatly polished surface, and the second interlayer insulating film. A second wiring layer formed on the surface of the insulating film. here,
The thickness of the SOG layer is 1/5 to 1/3 of the thickness of the first wiring layer.
The film thickness is preferably Further, the method for manufacturing a semiconductor device of the present invention includes a step of forming a first wiring layer on a semiconductor substrate via an insulating film, and a step of forming a first interlayer insulating film on the first wiring layer. , SOG on the first interlayer insulating film
A step of applying a layer, a step of forming a second insulating film on the SOG layer, a step of planarizing the surface of the second interlayer insulating film using a CMP method, and a surface of the second interlayer insulating film. Second on top
And the step of forming the wiring layer. Where SOG
The layer is preferably formed by coating so as to have a thickness of 1/5 to 1/3 of that of the first metal wiring. The second interlayer insulating film is formed thicker than the first metal wiring. Furthermore, it is preferable to include a step of removing the SOG layer on the first wiring layer by etching back after forming the SOG layer.

[0008]

Next, the present invention will be described with reference to the drawings. 1 and 2 are sectional views showing a first embodiment of the manufacturing method of the present invention in the order of manufacturing steps. First, as shown in FIG. 1A, the surface of a semiconductor substrate 11 made of single crystal silicon is thermally oxidized to form a base insulating film 12 made of a silicon oxide film. An aluminum alloy is formed on the base insulating film 12.
For example, an Al-Si-Cu alloy film is formed by a sputtering method.
The first metal wiring 13 is formed by forming the film with a thickness of 00 nm and selectively etching the alloy film by using the photolithography technique. Then, a first interlayer insulating film 14, for example, a silicon oxide film is formed on the first metal wiring 13 by CVD.
To a thickness of 300 nm using the
3 and the surface of the base insulating film 12 are covered.

Then, as shown in FIG. 1B, an organic solution containing silicon is spin-coated on the first interlayer insulating film 14,
Then, heat treatment is performed to form the SOG layer 15. This SO
The thickness of the G layer 15 is 1/5 to 1 of that of the first metal wiring 13.
It is formed with a thickness of / 3, and is formed here with a film thickness of 100 nm. As a result, the SOG layer 15 is applied in an area having a wide interval between the first metal wirings 13 to the same thickness as described above, but the SOG layer 15 is applied in an area having a narrow spacing between the first metal wires 13 as described above. The SOG layer 15 alleviates the level difference of the narrow recesses formed between the first metal wirings 13.

Subsequently, as shown in FIG. 1C, the SOG
A second interlayer insulating film 16 is formed on the layer 15 by using the CVD method.
For example, a silicon oxide film is formed sufficiently thick. This second
The thickness of the interlayer insulating film 16 is at least the first metal wiring 1
It is preferable that the thickness is thicker than that of No. 3 and twice or more. In this embodiment, it is formed with a film thickness of 1300 nm. Then, as shown in FIG. 2A, the second interlayer insulating film 16 is polished by the CMP method to flatten the surface.
Here, polishing is performed to about 700 nm. This allows the second
The surface of the interlayer insulating film 16 is flattened in both the region where the first metal wiring 13 is present and the region where it is not present.

After that, as shown in FIG. 2B, the first metal wiring 13 is formed at a required position through the second interlayer insulating film 16, the SOG layer 15, and the first interlayer insulating film 14 by using a photolithography technique. A through hole 17 that reaches up to is formed. Then, as shown in FIG. 2C, a metal film of an Al alloy having a film thickness of 500 nm is formed on the second interlayer insulating film 16 by a sputtering technique, and this is selectively etched by a photolithography technique. The second metal wiring 18 is formed. The second metal wiring 18 is the through hole 1
It goes without saying that it can be electrically connected to the first metal wiring 13 through 7.

Therefore, in the multilayer wiring structure of the semiconductor device manufactured as described above, by forming the SOG layer 15 on the first interlayer insulating film 14, the first metal wiring 1 is formed.
The SOG layer 15 can mitigate the step difference in the portion where the distance 3 is narrow. Therefore, the second interlayer insulating film 16 is formed thereon.
When the second interlayer insulating film 16 is formed, there is no occurrence of “mark” when the second interlayer insulating film 16 is grown, and therefore, when the second interlayer insulating film 16 is subsequently polished by the CMP method. No concave groove is generated.

Further, although the SOG layer 15 is formed, since this film thickness is as thin as about 1/5 to 1/3 of the film thickness of the first metal wiring 13, cracks are hardly generated, The reliability of the interlayer insulating film of the manufactured semiconductor device is not lowered. Further, since the second interlayer insulating film 16 is formed sufficiently thicker than the first metal wiring 13, the CMP is performed.
A large polishing margin for planarization by the method can be taken, the film thickness of the interlayer insulating film in the region where the first metal wiring 13 does not exist can be prevented from being reduced, and the photolithography technique in the subsequent step can be used. A large focus margin can be secured.

3 and 4 are sectional views showing a second embodiment of the manufacturing method of the present invention in the order of manufacturing steps. As shown in FIG. 3A, first, a base insulating film 22 is formed on a semiconductor substrate 21 made of single crystal silicon as in Example 1, and a first Al alloy film having a thickness of 500 nm is formed on the base insulating film 22. The metal wiring 23 is formed. Further, a first interlayer insulating film 24 is formed to a thickness of 300 nm on this first metal wiring by using the CVD method. Then, as shown in FIG. 3B, an organic solution containing silicon is spin-coated and heat-treated to form the SOG layer 25 so that the film thickness of the flat portion is 100 nm.

Moreover, here, as shown in FIG.
The SOG layer 25 is etched by using a dry etching technique to remove the SOG layer 25 on the first metal wiring 23. At this time, since the thickness of the SOG layer 25 formed on the first metal wiring 23 is extremely smaller than the thickness of the SOG layer 25 embedded in the narrow gap portion of the first metal wiring 23, Even if the part of the SOG layer 25 is removed, the embedded part of the SOG layer 25 is not completely removed, and the remaining SOG layer 25 alleviates the step difference of the concave portion between the first metal wirings 23. To be done.

Then, as shown in FIG. 4A, the CVD
The second interlayer insulating film 26 is formed to be sufficiently thick, here, to a film thickness of 1300 nm by using the method. And FIG. 4 (b)
As described above, the second interlayer insulating film 26 is formed by the CMP method.
The surface is flattened by polishing to about 00 nm. Furthermore,
As shown in FIG. 4C, the flattened second interlayer insulating film 2 is formed.
A through hole 27 is formed in 6 and a second metal wiring 28 is formed by sputtering or photolithography.
It is formed to a film thickness of 00 nm.

Also in the semiconductor device formed in the second embodiment, as in the first embodiment, the second interlayer insulating film 2 is formed.
It is possible to prevent the occurrence of concave grooves on the surface of 6 and the occurrence of cracks in the SOG layer 25, and it is possible to realize flattening of the multilayer wiring over the entire semiconductor device. In addition, since the SOG layer 25 on the first metal wiring 23 is removed by etching in the second embodiment, even when the through hole 27 is opened on the first metal wiring 23, the through hole 27 is formed.
Since the SOG layer 25 is not exposed inside,
Since the generation of degas from the layer 25 is suppressed, a good shape can be obtained in the through hole portion when the second metal wiring 26 is formed.

[0018]

As described above, according to the manufacturing method of the present invention, the first interlayer insulating film is formed on the first wiring layer, the SOG layer is formed thereon, and the second interlayer insulating film is further formed thereon. Since the interlayer insulating film is formed and then the surface of the second interlayer insulating film is polished flat to form the interlayer insulating film, the SOG layer alleviates irregularities in the first wiring layer, It is possible to prevent the generation of "sun" in the interlayer insulating film, and it is possible to prevent the formation of concave grooves on the surface polished by CMP. As a result, it is possible to prevent problems such as the entry of foreign matter into the concave groove, and it is possible to improve the reliability of the semiconductor device. Also, S
Since the OG layer is used to reduce the step difference between the first wiring layers, its film thickness is 1/5 to 1 / the thickness of the first wiring layer.
It can be as thin as 3 and can prevent cracks from occurring
It is also possible to improve the reliability of the G layer itself and the reliability of the second interlayer insulating film and the second wiring layer formed thereon.
Furthermore, since the second interlayer insulating film is formed to be sufficiently thicker than the first metal wiring, the second interlayer insulating film whose surface has been polished exists in the region where the first wiring layer exists. There is no difference in the thickness in the non-use region, and the entire semiconductor device can be planarized. As a result, it is of course possible to prevent disconnection in the first wiring layer, and it is possible to increase the focus margin in the photolithography technique.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the first half of a manufacturing process according to a first embodiment of the present invention in process order.

FIG. 2 is a cross-sectional view showing the latter half of the manufacturing process of the first embodiment of the present invention in process order.

FIG. 3 is a cross-sectional view showing the first half of the manufacturing process of the second embodiment of the present invention in process order.

FIG. 4 is a cross-sectional view showing the latter half of the manufacturing process of the second embodiment of the present invention in process order.

FIG. 5 is a cross-sectional view showing an example of a conventional manufacturing method in process order.

FIG. 6 is a cross-sectional view showing another example of the conventional manufacturing method in the order of steps.

[Explanation of symbols]

 11, 21 Semiconductor substrate 13, 23 First metal wiring 14, 24 First interlayer insulating film 15, 25 SOG layer 16, 26 Second interlayer insulating film 17, 27 Through hole 18, 28 Second metal wiring

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[Procedure amendment]

[Submission date] September 22, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

After that, as shown in FIG. 2B, the first metal wiring 13 is formed at a required position through the second interlayer insulating film 16, the SOG layer 15, and the first interlayer insulating film 14 by using a photolithography technique. A through hole 17 that reaches up to is formed. Then, as shown in FIG. 2C, a metal film of an Al alloy having a film thickness of 500 nm is formed on the second interlayer insulating film 16 by a sputtering technique, and this is selectively etched by a photolithography technique. The second metal wiring 18 is formed. The second metal wiring 18 is the through hole 1
It goes without saying that it is electrically connected to the first metal wiring 13 through 7.

Claims (6)

[Claims] 1. A first wiring layer, a first interlayer insulating film formed on this first wiring layer, an SOG layer formed on this first interlayer insulating film, and this SOG layer. A semiconductor device comprising: a second interlayer insulating film formed on the surface of which a surface is polished flat; and a second wiring layer formed on the surface of the second interlayer insulating film. 2. The semiconductor device according to claim 1, wherein the SOG layer has a film thickness that is ⅕ to ⅓ of the film thickness of the first wiring layer. 3. A step of forming a first wiring layer on a semiconductor substrate through an insulating film, a step of forming a first interlayer insulating film on the first wiring layer, and a step of forming the first interlayer A step of applying an SOG layer on the insulating film, a step of forming a second insulating film on the SOG layer, and a step of planarizing the surface of the second interlayer insulating film using a chemical mechanical polishing method. And a step of forming a second wiring layer on the surface of the second interlayer insulating film. 4. The SOG layer is 1/5 to 1 of the first metal wiring.
The method for manufacturing a semiconductor device according to claim 3, wherein the film is formed to have a thickness of / 3. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the second interlayer insulating film is formed thicker than the first metal wiring. 6. The step of etching back after forming the SOG layer to remove the SOG layer on the first wiring layer.
6. A method of manufacturing a semiconductor device according to any one of 5 to 5.