JPS62291947A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To flatten the surface of an interlayer insulating film by a method wherein a resist pattern is provided surrounding the protruded region of the interlayer insulating film on a wide-widthed wiring in the height same as that of the protruded region, a resist is coated thereon, and the resist and the insulating film are etched away at the same speed of etching. CONSTITUTION:Al wirings 3-5 are provided on an Si substrate 1, and an SiO2 film 6 is formed by performing a bias sputtering method. A resist pattern 7 is formed surrounding the protruded part 6 left on the wide-widthed wiring 3 in the same height as the protruded part 6. Then, a resist 8 is coated on the whole surface. When anisotropic etching is performed under the prescribed pressure using the mixed gas of CHF3+C2F6+O2, the resists 7 and 8 and the SiO2 film 6 are etched away at the same speed of etching, and a flat surface is obtained. Then, windows 9 and 9' are provided, and an Al wiring 10 is attached. As the thickness of an interlayer insulating film becomes same on the wiring irrespective of the width of the Al wiring, the non-uniformity in the condition of formation of windows caused by the irregularity in film thickness can be removed, and the number of unsatisfactory connections can also be reduced.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention Industrial Applications The present invention relates to a method for manufacturing a multilayer wiring structure in a semiconductor device, particularly a multilayer wiring structure having an interlayer insulating film with a flattened surface. It is.

BACKGROUND OF THE INVENTION As the element dimensions of semiconductor devices, particularly semiconductor integrated circuit devices, become smaller, the line width and line spacing of aluminum interconnects in multilayer interconnect structures tend to become narrower and narrower. Bias sputtering is a method for forming an interlayer insulating film between aluminum wiring layers in such a multilayer wiring structure by applying a high-frequency voltage to the substrate, which allows the insulating film to be buried between narrow interconnections without creating voids. This method has a feature not found in other forming methods, in that it can substantially flatten the surface of an insulating film formed on aluminum wiring with a fine line width.

Problems to be Solved by the Invention However, the bias sputtering method has traditionally had problems as shown in FIG.
There were problems as shown in the cross-sectional view of %/c.

In FIG. 4, a film 2 of Sin is formed on the surface of a semiconductor substrate 1.
is formed, and aluminum interconnections 3, 4.6 are formed thereon. When the bias sputtered 5102 film 6 is formed on the aluminum wiring under appropriate conditions as in Part 4, the surface of the 5102 film on the wiring 3 with a narrow line width becomes flat, but when the line width becomes wider, the wiring As seen above 4 and 6, small protrusions 11 and protrusions 12 remain, and 51
02 film 6 cannot be made completely flat.

In the bias sputtering method, the etching rate of 5102 due to the high frequency bias is higher than the deposition rate of 5102 flying from the target on the slope 18. As a result, for example, in the wiring 6, the slope 18 recedes inward from both ends thereof. go.

Then, within the time required to form the film 6 to a predetermined thickness, the slope of 5i02 that initially existed on the wiring 3 is completely removed by etching from both ends, but the slope of the wiring 3 is completely removed. In this case, the protrusion 11 remains because it is in the state just before completion, and the slope 1 remains because the wiring 6 has not finished at all.
A convex portion with 8 remains. In order to remove the convex portion of the wide wiring 5, it is possible to retreat the slope 18 and continue bias sputtering until it is completely removed, but this takes an extremely long time and poses a serious problem in practice. , After forming the interlayer insulating film 6, the second layer aluminum wiring and the first layer
In order to connect the layered aluminum wiring, it is necessary to open a contact window in the membrane 6. FIG. 4 is a cross-sectional view when the film 6 is selectively removed by the thickness of the 5-inch film 6 existing on the surface area of the wiring 4, and a contact window 9.9' is opened on the wiring 4.6. . In this case, 5i on wiring 4
Since the n2 film has the protrusion 11, when etching is performed by an amount corresponding to the thickness of the 5102 film 6, the SiO2 protrusion 11' remains inside the contact window 9. Furthermore, since the SiO2 film on the wiring 6 is considerably thicker than on the wiring 4, the bottom surface of the contact window 9' remains 5in2, and
The surface is not exposed. Therefore, the situation shown in FIG. 4 causes a problem of contact failure between wiring layers. To avoid contact failure,
As shown in FIG. 4C, it is only necessary to selectively remove the 5i02 film 6 by an amount corresponding to the thickness of the 5io2 film on the wiring 5, but as a result, the 5102 film on the thin wiring 4 is considerably removed. Overetching occurs, and the surface of the wiring 40 is partially removed, and in some cases, the wiring film 4 existing in the area of the contact window 9 is completely removed, causing a contact failure with the second aluminum wiring layer again. This may cause some inconvenience. In short, the conventional method of forming an interlayer insulating film using bias sputtering has the disadvantage that a convex portion remains partially on the surface of the insulating film on the wiring, resulting in imbalance in the etching of the contact window.

Means for Solving the Problems The present invention has been made to solve the problems of the interlayer insulating film formed by the conventional bias sputtering method. After forming the film, for example, a photoresist film pattern with a thickness approximately equal to the height of the convex region is provided around the entire convex region of the interlayer insulating film remaining on the wide wiring, and the interlayer insulating film is Further, on the convex regions of the insulating film and the above-mentioned photoresist pattern, a flowable photoresist, for example, is applied again to flatten the entire surface, and under conditions such that the etching rate of the photoresist and the interlayer insulating film are almost the same. This method uniformly etches downward from the resist surface, which has been flattened with trenches where the convex regions disappear.

Effect: Providing a photoresist film pattern having almost the same thickness surrounding the convex region of the interlayer insulating film formed by the bias sputtering method as in the present invention means that the surface of the convex region and the seven areas around it are provided. It serves to align the surfaces of the photoresist film patterns to approximately the same height. In this state, a groove is formed between the edge of the photoresist film and the edge of the convex area.
This groove can be filled by applying photoresist again, so that the initially convex surface becomes completely flat. Next, the surface planarized in this way is etched. In the method of the present invention, conditions are selected so that the etching speed of the photoresist film and the interlayer insulating film are approximately equal, so the photoresist film and the interlayer insulation film are etched. Even if the surface of the insulating film is exposed at the same time, the surface will be removed while maintaining its flatness, and if etching is finished when all the convex parts of the interlayer insulating film are removed, the entire surface area of the interlayer insulating film will be removed. It becomes flat throughout.

EXAMPLES The manufacturing method of the present invention described above will be specifically explained using examples.

(Example 1) FIGS. 1 &-6 are cross-sectional views showing the process of forming a two-layer wiring using the manufacturing method according to the present invention.

In the process shown in FIG.
is provided. The thickness of the aluminum wiring is 0.6 μm, and in wiring 3, the line width is 0.5 μm and the interval is 0.6 μm.
One wiring 4 has a line width of 2 μm, and one wiring 6 has a line width of 10 μm.

When a 5i02 film 6 is formed on this wiring using a film forming method that applies high frequency to the substrate, such as bias sputtering, the 8102 film 6 above it is automatically flattened, especially in the wiring 3 with a small line width. The 5i02 film 6 can be embedded even between narrow interconnections without creating voids (step shown in FIG. 1). The thickness of the 5i02 film 6 is 0 on the surface of the wiring 3.
．． 7Afn, 1.2ttm on 5io2 membrane 2.

The thickness on the surface of the wiring 6 is 1.2 μm. After forming the film 6, a photoresist pattern 7 with a thickness of 065 μm was formed to surround the convex portion remaining on the wide aluminum wiring 6.
Furthermore, a photoresist film 8 is uniformly applied to the entire surface to a thickness sufficient to flatten the surface of the film 8 (step C in FIG. 1). Next, under the conditions that the etching speed of the 5i02 film 6 and the resist 7.8 are the same, the convex portions of the resist 7 and 8.5in2 film 6 are removed, and the surface of the 8102 film 6 becomes flat (step d in Figure 1). ). Such etching can be carried out, for example, using a mixed gas C)IF, (20SCCM)/C2F6(6
SCCM) 10,2 (3SCCM) (flow rate in parentheses) and pressure 13.3 p2L. After the process shown in FIG. 1d, contact windows 9.9'
Open it and install the second layer of aluminum wiring 1o.
process). Here, according to the process Q (1) according to the present invention, the thickness of the 8102 film 6 on the wiring 4.6 is equal to o, 7μ
m, the etching conditions for 5i02 when opening the contact windows 9,9' can be made exactly the same, and an unbalance in the etching conditions as seen in the prior art does not occur.

(Example 2) As a second embodiment, the steps shown in FIGS. 2a and 2b are also possible.

In the second step, after forming aluminum wirings 3 and 4.5 with a thickness of 0.6 μm, sputtering is performed while applying a bias voltage to the substrate to form the first interlayer insulating film.
The iO2 film 13 is formed to have the same film thickness as the 13J31416 or slightly thicker (20.5 μm), but the surface shape of the 5102 film 13 formed under these conditions is similar to that of the wiring 3 with a narrow line width as shown in Figure 2. It has not yet been flattened.

A voltage lower than the bias voltage used for forming the 5102 film 13 is applied to the surface of the 5102 film 13, or sputtering is performed with or without bias to form a second interlayer insulating SiO
Two films 14 are formed to have a thickness of 0.7 μm. Kita○2 Membrane 14
However, a photoresist pattern 16 with a film thickness of 0.5 μm is provided around all the convex regions except for the convex portion of the interconnect 3 due to the narrow wiring interval, and then the entire surface is coated. A photoresist film 16 is applied across the film 9 and 7 to an appropriate thickness.

When coating film 16, it has fluidity and can be applied even between the narrow wiring lines 3.
6 is filled, so that the surface of the film 16 becomes flat (step shown in Figure 2). After this, 7 Otoresist 16.16.5102
The film 16 is etched under conditions that the etching rates of the film 14 are approximately equal.
By etching the surface of the film 14 to eliminate the convex portions of the film 14, the surface of the interlayer insulating film 5102 can be made flat.

(Example 3) The process of Example 2 can be carried out by changing the 1:1 ratio of the process as shown in FIGS. 3a and 3b. In the third step, sputtering is first performed on the entire surface including the aluminum wirings 3 and 4.5 while applying a bias voltage to the substrate.
Same as 4.6 or slightly thicker (20.68m)
) 5i02 film 13 is formed. After this, the 5-inch area created by sputtering was
2 Around the convex part of the membrane 13, a layer 1 with a thickness approximately equal to the height of the convex part is placed.
Seven photoresist patterns 16 of 5 μm are formed, and a photoresist film 16 of an appropriate thickness is further coated to form the film 1.
60 Flatten the surface. Next, in the step shown in Figure 3,
Etching is performed uniformly over the entire surface of the film 16 under conditions such that the etching rates of the photoresist film 16 and the 5in2 film 13 are almost equal, and when the etching is finished when the convex portions of the film 13 disappear, the surface is etched. Become flat. After that, the SiO2 film 1 was formed by sputtering without applying a bias to the substrate.
By forming 7 to a thickness of 0.7 μm, an interlayer insulating film 5i02 is completed.

In the above embodiments, a bias-applied sputtering method was used to form the interlayer insulating film, but when a substrate bias is applied to form the insulating film, it is sufficient that the insulating film is buried between narrow interconnections, and a bias-applied normal pressure CV method is used. Law.

LPCVD method, plus-r CVD method, IEC
R plasma CVD method can also be used. , and the photoresist film used for planarization was SiO□, S
Other materials such as iNx may be used, and in particular, as a substitute for the second 7 photoresist film, highly fluid spin-on glass such as an alcoholic solution of an organic compound of Si may also be used. Furthermore, it goes without saying that the present invention can be applied to interlayer insulating film materials other than 5102.

Effects of the Invention As described above, the present invention is particularly useful in the process of forming an interlayer insulating film in a multilayer wiring structure, in addition to applying a bias as conventionally done to form an interlayer insulating film. The convex areas of the above-mentioned insulating film remaining on the wide wiring are almost completely removed by covering with a fluid film such as photoresist and etching, and the surface of the interlayer insulating film is flattened. The thickness of the interlayer insulating film existing on the wiring is all made the same regardless of the line width of the wiring. This eliminates the conventional problem of unbalanced contact window etching conditions caused by variations in interlayer insulating film thickness on interconnects of different widths, prevents contact defects, and improves the manufacturing yield of semiconductor devices with multilayer interconnects. This contributes to

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing a multilayer wiring manufacturing method according to a first embodiment of the present invention, FIG. 2 is a process cross-sectional view showing a method according to a second embodiment of the present invention, and FIG. FIG. 4 is a process cross-sectional view showing an example method. FIG. 4 is a cross-sectional view for explaining problems with an interlayer insulating film formed by a conventional bias sputtering method. 1...Silicon substrate, 2...5in2
Film, 3.4°5...First layer aluminum wiring, 6,1
3,14.17...Bias sputtering 5i02
Film, 7, 8, 16° 16...Photoresist, 9, 9'...Contact window, 10...
...Second layer aluminum wiring, 11...SiO2
Protrusion of film, 12...Protrusion of SiO2 film, 18.
...Slope of bias sputtered 5i02 film. Name of agent: Patent attorney Toshio Nakao, 1st person, 2nd person
Figure 3

Claims (1)

[Claims] forming an insulating film on a region including at least a wiring on a semiconductor substrate while applying a bias voltage to the semiconductor substrate; A step of forming a first film pattern having a film thickness approximately equal to the height of the convex portion, and a step of forming a second film having fluidity so as to cover the convex portion and the first film so as to cover almost the entire surface. In the flattening step, the entire area including the convex portion of the insulating film and the first and second films is etched into a desired area under conditions such that the etching rates of the insulating film and the first and second films are approximately equal. A method for manufacturing a semiconductor device comprising a step of uniformly etching away only the amount.