JPH02215123A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make connecting holes without excessive etching process by a method wherein a flat surfaced etching mask is applied to an insulating layer on a substrate for making openings; the openings are filled up with a material whose volume is to be reduced by setting; and after the setting process, the setting material and the insulating layer are successively removed. CONSTITUTION:A resist mask 5 with openings 6, 7 is provided on an Si substrate 1 covered with a PSG layer 4 having wirings 2, 3 and diffused layers 8. When a spin on glass layer 9 is applied to the whole surface and dried up, the volume of the layer 9 is reduced to 30% turning into a coated layer 19. When plasma-etched using CHF3, the layers 10, 4 both comprising SiO2 are etched away at the same rate. The time required for the complete connection equals the sum of the film thickness of both layers 10 and 4. In such a constitution, the difference in the thickness of the PSG layer 4 can be decreased by the spin on glass layer 10 so that the excessive etching of the substrate 1 may be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device, particularly a method of forming a contact hole in a semiconductor device.

The purpose is to reduce excessive etching of the underlying layer that occurs when forming contact holes in an insulating layer that has a layer thickness distribution.

a step of forming an insulating layer covering one surface of the substrate on which a conductive region is formed; a step of forming an etching mask layer having a flattened surface on the insulating layer; and a step of forming an etching mask layer on a predetermined region of the etching mask layer. forming an opening that reaches the insulating layer; depositing a small amount of material (which decreases in volume when solidified in the opening); solidifying the material; forming a contact hole reaching the conductive region by sequentially removing the solidified material layer and the insulating layer in the opening using an etching means capable of etching the solidified material layer. TECHNICAL FIELD The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a contact hole in a semiconductor device.

[Conventional technology]

2. Description of the Related Art As semiconductor devices become more highly integrated, multilayer wiring structures are used, and as a result, the level difference between a portion of a wiring layer and a region around it on a substrate surface becomes significant. The thickness of the insulating layer formed on the substrate surface in the vicinity of such a large step difference tends to be larger than the thickness of the insulating layer in a region away from one step.

Such non-uniformity in layer thickness distribution is noticeable in insulating layers such as PSG (phosphosilicate glass), which are subjected to reflow treatment after deposition, and is especially noticeable when wiring patterns are placed close together. The thickness of the insulating layer increases.

[Problem to be solved by the invention]

For example, as shown in FIG. 3, wiring layers 2 and 3 made of a polycrystalline silicon layer with a thickness of about 1 μm are formed on a silicon substrate 1.
are formed, and on these wiring layers 2 and 3,
An interlayer insulating layer 4 made of PSG with a thickness of approximately 1 μm is formed, and contact holes are formed in the glabella insulating layer 4 in the region between wiring layers 2 and 3, indicated by symbol A, and in the region away from the wiring layer 2, indicated by symbol B. Assume that a

When the distance between the wiring layers 2 and 3 is close to 2, for example, about 2 μm, the thickness of the glabella insulating layer 4 in area A is 1.5 μm.
It will be about m. On the other hand, the thickness of the glabella insulating layer 4 in the region B away from the wiring layer 2 is a predetermined value of 11 Im.

A resist layer 5 is coated and formed on the glabellar insulation M4 having such a layer thickness distribution.

This is patterned by a predetermined lithographic process to provide openings 6 and 7 in the two-head mounts A and B, respectively.

In addition, the glabellar insulating layer 4 and the resist layer 5 in each part
The thickness is as illustrated in the figure.

When the glabellar insulating layer 4 exposed in the openings 6 and 7 is dry-etched using, for example, CHF, using the resist layer 5 as a mask, a contact hole is quickly formed in region B, and then a contact hole is formed in region A. The silicon substrate 1 is etched during the period until it is formed. That is, in region B, the silicon substrate 1 is excessively etched. If a large etching selectivity can be obtained between the silicon substrate 1 and the interlayer insulating layer 4.

This kind of inconvenience can be avoided usually by 2.

PSG and silicon substrate 1 used as glabellar insulating layer 4
The selectivity ratio is limited to about 5 to 10:1.

On the other hand, the depth of the diffusion layer 8 directly under the contact hole is 8, for example, 256 bits/chip DRAM or E
The source/drain region of a MOS transistor constituting a FROM is approximately 0.3 μm, and the thickness tends to become even shallower as integrated circuits become more sophisticated and denser. Therefore, if excessive etching of the silicon substrate 1 occurs as described above, the thickness of the diffusion layer decreases, which may seriously affect the characteristics such as an increase in resistance and an increase in leakage current. In extreme cases, the diffusion layer disappears and the semiconductor device ceases to function.

The present invention occurs when a contact hole is formed in a glabellar insulating layer having the above layer thickness distribution. The purpose is to reduce excessive etching of the base.

[Solve the problem! Method of cooking〕

The above objects include a step of forming an insulating layer covering one surface of a substrate on which conductive regions are formed, a step of forming an etching mask layer having a flattened surface on the insulating layer, and a step of forming an etching mask layer on the insulating layer. forming an opening reaching the insulating layer in a predetermined region; depositing a substance whose volume decreases when solidified into at least the opening; solidifying the substance; forming a contact hole reaching the conductive region by sequentially removing the solidified material layer and the insulating layer within the opening using an etching means capable of etching the solidified material layer; This is achieved by the method for manufacturing a semiconductor device according to the present invention, which is characterized by the following.

[For production]

For insulating layer surfaces that have unevenness due to layer thickness distribution.

For example, when a resist solution is applied by a method such as spin coating, a thick resist layer is formed on the concave portions and a thin resist layer is formed on the convex portions. Therefore, when openings are provided in such a resist layer, shallow openings are formed in the convex portions, while deep openings are formed in the concave portions.

When a coating solution that forms a SiO□ layer after drying, such as spin-on glass, is applied to the surface of the insulating layer on which a resist layer with openings as described above is formed, a thin 5i02 layer is formed in the shallow openings. , in the deep opening there is a thick 5
An iOz layer remains. That is, a thin Si02 layer is formed on the thick insulating layer in the convex portions, and a thick 5ioz Jif layer is formed on the thin insulating layer in the concave portions. Therefore, the difference in the sum of the layer thicknesses of the 5i02 layer and the underlying insulating layer in the convex portion and the concave portion is smaller than the difference in the layer thickness of the insulating layer before coating the spin-on glass, and the excessive etching of the substrate as described above is is reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In the following drawings, the same parts as in the previously shown drawings are designated by the same reference numerals.

Referring to FIG. 1(a), wires H2 and 3 are connected in advance.
A resist is applied onto the silicon substrate 1 on which a diffusion layer 8 is formed and an interlayer insulating layer 4 made of PSG is formed to form an etching mask layer 5. and 1 using normal glue sogelaf technique.

Openings 6 and 7 corresponding to the diffusion layer 8 are formed in the resist layer 5.

Next, spin-on glass is applied to the entire surface of the silicon substrate 1 on which the etching mask layer 5 is formed using an 8-spin coating method. In the figure, reference numeral 9 indicates the spin-on glass layer 9 immediately after coating.

Next, a predetermined baking process is performed to dry the spin-on glass layer 9. When the solvent is removed by drying, the volume of the spin-on glass layer 9 is reduced to about 30%. 1st
Figure (b) shows the state after the above baking process, with reference numeral 1
0 indicates a coating layer 10 made of spin-on glass.

As mentioned above, the spin-on glass layer 9 is formed by baking.
The volume of is reduced by 30%. therefore.

If the thickness of the spin-on glass layer 9 immediately after coating on the etching mask layer 5 is 0.3 μm, the thickness of the spin-on glass layer 10 after baking is 0.09 μm on the etching mask layer 5, openings 6 and 7. Inside,
They are 0.42 μm and 0.57 μm, respectively.

In the state shown in FIG. 1 et al., the spin-on glass layer IO in the openings 6 and 7 and the underlying glabellar insulating layer 4 are etched using the etching mask layer 5 as a mask. For this etching, plasma etching using, for example, CHP3 gas as an etching agent is used. The spin-on glass layer 10 and the interlayer insulating layer 4 are both made of SiO□ and are etched at approximately the same rate.

The ratio of the time taken to selectively remove the opening 6 and the open lower spin-on glass layer 10 and the interlayer insulating layer 4 until a contact hole is formed in each is approximately equal to the ratio of the sum of the layer thicknesses in each. That is, 1.92/1.57
=1.22. On the other hand, when etching is performed in the state shown in FIG. 2 without providing the spin-on glass layer 10, 1.5/1.0=1.5.

Therefore, in this etching, if the etching selectivity ratio of the interlayer insulating layer 4 to the silicon substrate 1 is 10, the excessive etching depth of the silicon substrate 1 in the region B when a contact hole is formed in the region A is as follows.
It becomes 0.02 μm. On the other hand, when the spin-on glass layer 10 as shown in FIG. 2 is not provided, the excessive etching depth is 0.05 μm, and the excessive etching is reduced by the method of the present invention.

In the above embodiment, for example, a layer of SiO□ is additionally formed in the openings 6 and 7.

Although spin-on glass is used as a substance that causes volumetric shrinkage upon drying, cysts may be used instead of spin-on glass, since the volume decreases by about 20% upon drying. Such a resist solution can be obtained by diluting an ordinary resist by adding a solvent. Furthermore, the method of the present invention is not limited to the formation of contact holes for the diffusion layer formed on the substrate as in the above embodiments, but can also be applied to the formation of contact holes for lower layer wiring.

In the present invention, the reason why a solution causing volume contraction as described above is used is due to the etching selectivity between the PSG layer and the etching mask N5.

That is, if a solution that does not shrink in volume at all is applied instead of spin-on glass, the thickness of the coating layer in openings 6 and 7 will be equal to the depth of openings 6 and 7, and contact holes will be formed in openings 6 and 7 at the same time. Therefore, the problem of excessive etching of the silicon substrate 1 does not occur.

However, according to the above method, if a solution that does not undergo volumetric contraction is used, there is a problem that the thickness of the etching mask layer becomes excessively large. That is, the etching mask layer 5 is a layer that can function as a mask at its thinnest portion, such as on the wiring layer 2 or 3, while the coating layer in the openings 6 and 7 and the underlying interlayer insulating layer 4 are etched away. It must be thick. Since the etching selectivity ratio between PSG or SiO□ and resist is usually about 2:1, the minimum thickness of the etching mask layer 5 in the case of the layer thickness distribution shown in FIG. 1 is 2.5 μm in region A. It is 2 μm on wiring layer 2 or 3, and 3 μl on region B.

In reality, due to variations in the thickness of the resist mask layer 5, the resist mask layer 5 is formed approximately 0.3 μm thicker than the above value.

However, in order to form fine contact holes, it is necessary to make the layer thickness of the etching mask layer 5 as small as possible, and the maximum limit for forming contact holes of about 1 μm square is usually 2.0 μm. has been done. Therefore, the thickness of the etching mask layer 5 as described above cannot be adopted in reality. As a result, the etching mask layer 5 must be made to have a practical thickness, and the thickness of the coating layer must be reduced accordingly.

In the above embodiments, spin-on glass was used as the volume-shrinking substance to be filled into the opening, or such a material does not have to be a material made by solidifying a solution; May be used.

〔Effect of the invention〕

According to the present invention, it is possible to reduce excessive etching of a semiconductor substrate that occurs when contact holes are formed in an insulating layer having irregularities, and there is an effect that semiconductor devices having desired characteristics can be manufactured with high yield.

5 is an etching mask layer.

6 and 7 are openings.

8 is a diffusion layer.

9 is the spin-on glass layer immediately after coating.

10 is the spin-on glass layer after drying It is.

[Brief explanation of the drawing]

FIG. 1 is a detailed explanatory diagram of the present invention. Figure 2 is a diagram explaining the problems of the conventional method. It is. In fig. 1 is a silicon substrate. 2 and 3 are wiring layers. 4 is the insulating layer between the eyebrows. Akira Suekabuto's search for Tommen Akira Dan So-called figure (Part 1) Suekocho's remanufacturing method Myotorou passion 1 Diagram (t no 2) Diagram explaining the problems of delivery Father-in-law group

Claims (1)

[Claims] A step of forming an insulating layer covering one surface of a substrate on which a conductive region is formed; a step of forming an etching mask layer having a flattened surface on the insulating layer; and a step of forming an etching mask layer on the insulating layer. forming an opening in a predetermined region of the layer to reach the insulating layer; depositing a substance whose volume decreases when solidified in at least the opening; solidifying the substance; forming a contact hole reaching the conductive region by sequentially removing the solidified material layer and the insulating layer in the opening using an etching means capable of etching the solidified material layer and the solidified material layer; A method of manufacturing a semiconductor device, comprising: