JPH09102543A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method by which a sufficiently high smoothness can be obtained regardless of the wiring interval and wiring layout without using any special mask, etc. SOLUTION: A semiconductor device manufacturing method includes a first smoothing process and a second smoothing process for smoothing the interlayer insulating film between wiring layers and the first smoothing process is composed of a step S1 for forming a lower wiring layer on a substrate, a step S2 for forming a first insulating film on the lower wiring layer, a step S3 for applying an SOG to the surface of the first insulating film, and a step S4 for flattening the surface of the SOG by etching back the SOG. The second smoothing process is composed of a step S5 for forming a second insulating film on the surface of the substrate after the SOG is etched back, a step S6 for applying a flattening material to the surface of the second insulating film, a step S7 for etching back the flattening material, a step S8 for forming an interlayer insulating film on the surface of the substrate after the applied flattening material is etched back, and a step S9 for forming an upper wiring layer on the interlayer insulating film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a smoothing method between wiring layers in a multilayer wiring structure.

[0002]

2. Description of the Related Art An interlayer insulating film of a semiconductor device having a multi-layer wiring structure needs to be smoothed as much as possible in order to improve the coverage of a wiring layer. As a method of smoothing this interlayer film,
Resist coating or S which is a liquid silica compound
A method of flattening the interlayer film surface by applying OG (Spin On Glass) on the interlayer insulating film and etching back the same to fill the recesses has been used.

FIG. 4 shows a flow chart of a conventional multi-layer wiring forming process of a semiconductor device using such a smoothing method. 5A to 5C are sectional views of the substrate showing the steps in this flow in order. In each drawing, the left side on the substrate shows a portion with a narrow wiring interval, and the right side shows a portion with a wide wiring interval.

First, the aluminum wiring 12 is formed on the silicon substrate 11.
Are formed by patterning (step S11). Next, the oxide insulating film 13 is formed so as to cover the aluminum wiring 12 (step S12). Then, SOG 14 is applied to the entire surface of the oxide insulating film 13 (step S13). The state thus far is shown in the cross section of FIG.

Next, the entire surface of the SOG 14 is etched back to flatten the surface, leaving the SOG 14 in the recesses between the wirings. This state is shown in FIG.

Subsequently, an interlayer insulating film 15 made of an oxide film or a silicon nitride film (P-SiN) is formed on the surface of the substrate after the SOG etch back (step S15). Next, the upper aluminum wiring 16 is patterned on the interlayer insulating film 15 (step S16). This state is shown in FIG.
It is shown in (C).

[0007]

However, in the conventional interlayer film smoothing method described above, process conditions are generally aimed at smoothing by embedding the portion of the minimum wiring interval, which generally deteriorates the step coverage. Is set. Therefore, the S
The OG is excessively etched back, and as shown in FIG. 5B, a large step D is formed on the surface of the insulating film 13 in the portion between the wiring portions. Therefore, the interlayer insulating film 15
When the aluminum wiring 16 is formed after the formation, a large recess 16a is formed in the aluminum wiring 16 as shown in FIG. 5C, flattening is not achieved, and a wiring pattern having stable characteristics cannot be obtained.

In order to deal with the deterioration of smoothness due to the wide and narrow wiring intervals, a dummy pattern made of an insulating film such as an oxide film or aluminum (Al) is provided in a portion with a wide wiring interval to make it pseudo. Attempts have been made to improve the overall smoothness by aligning the wiring intervals.
However, the provision of such a dummy pattern restricts the layout of the mask, complicates the pattern, and increases the labor of mask production.

The present invention has been made in view of the above-mentioned drawbacks of the prior art, and it is a method of manufacturing a semiconductor device in which sufficient smoothness can be obtained irrespective of the width of wiring and the layout of wiring without using a special mask or the like. For the purpose of providing.

[0010]

To achieve the above object, the present invention comprises a first smoothing step for smoothing an interlayer insulating film between wiring layers and a second smoothing step following the first smoothing step. The first smoothing step includes: (a) forming a lower layer wiring on the substrate; (b) forming a first insulating film on the lower layer wiring; and (c) SO on the first insulating film.
G is applied, and (d) SOG is etched back to flatten the surface. The second smoothing step includes (e) the second insulating film on the substrate surface after the SOG etchback. And (f) the second step
Applying a planarizing coating material on the insulating film,
(G) etching back the flattening coating material; (h) forming an interlayer insulating film on the substrate surface after the flattening coating material is etched back; and (i) on the interlayer insulating film. And a step of forming an upper layer wiring on the substrate.

In a preferred embodiment, the first insulating film in the first smoothing step is made of an oxide film type insulating material containing Si.

In another preferred embodiment, the second
The second insulating film in the smoothing step is characterized by being made of a Si nitride film.

In still another preferred embodiment, the flattening coating material in the second smoothing step is a resist.

In still another preferred embodiment, the second insulating film in the second smoothing step is formed to have a thickness equal to or larger than a film thickness corresponding to the maximum step formed after the SOG etch back. I am trying.

In yet another preferred embodiment, the SOG etchback in the first smoothing step is SOG /
It is characterized in that the etching selection ratio of the base insulating film is about 0.7 to 1.3.

In still another preferred embodiment, the etching back of the planarizing coating material in the second smoothing step has an etching selection ratio of the planarizing coating material / base silicon nitride film of about 0.7-. It is characterized in that the condition is 1.3.

By the first smoothing process using SOG, smoothing of a portion having a narrow wiring interval is sufficiently performed. Here, when a step is formed in a portion where the wiring interval is wide, the step is sufficiently smoothed by the second smoothing step, and the entire flattening is achieved.

On the lower layer aluminum wiring, a TEOS (T) film formed by plasma CVD, for example, is formed as a first insulating film.
Etra Ethoxy Silane) or CV
SiO2 due to D is formed. TEOS liquid at room temperature
Is decomposed by heat treatment into a Si oxide film. For these oxide-based insulating films, it is easy to set conditions for the selection ratio of the etching rate with SOG in the SOG etchback in the next step.

In the second smoothing step, a silicon nitride film such as plasma nitride (P-SiN) is formed as a second insulating film on the substrate surface after SOG etch back. Such a silicon nitride film has a strong blocking ability against Na contamination and moisture permeation, and is formed by plasma CVD.

A resist is applied as a planarizing coating material on the silicon nitride film. In this resist, it is easy to set the conditions for the selection ratio of the etching rate with respect to the silicon nitride film in the next etch back step.

In this case, it is desirable that the silicon nitride film is formed with a film thickness larger than the maximum step difference caused by the SOG etchback in the previous step. As a result, at the time of resist etch back in the second smoothing step, the maximum step portion is sufficiently filled with the silicon nitride film to achieve the flattening.

In etching back SOG and resist, the selection ratio to the underlying insulating film and silicon nitride film is 0.7 to 1.3, preferably about 1.
Set to. By setting such a selection ratio, a stable flattened shape can be obtained. When the selection ratio is 0.7 or less,
After the SOG or the thin portion of the resist is exposed at the protruding portion of the wiring pattern or the like, the etching of the underlying portion greatly advances, the wiring or the like is unnecessarily etched, and the reaction product gas or the like may cause characteristic deterioration. If the selection ratio is 1.3 or more, the etching rate of the SOG or the resist is too high as compared with the underlayer, and the SOG or the resist is excessively etched during overetching of the underlayer, and sufficient flatness cannot be obtained. . Therefore, the selection ratio is preferably 0.7 to 1.3.

[0023]

1 is a flow chart of a semiconductor manufacturing method according to an embodiment of the present invention. Further, FIGS. 2A to 2C and FIGS. 3D to 3F are substrate cross-sectional views sequentially showing different steps of the flow of this embodiment. In each drawing, the left side on the substrate shows a portion with a narrow wiring interval, and the right side shows a portion with a wide wiring interval.

The present invention is intended to smooth the interlayer insulating film in two steps. First, aluminum wiring 2 is patterned on a silicon substrate 1 on which a semiconductor element (not shown) is formed (step S1). Next, an oxide insulating film 3 is formed so as to cover the aluminum wiring 2 (step S2). The oxide insulating film 3 is made of, for example, SiO2 formed by CVD or a TEOS film formed by plasma CVD. Then, SOG4 is applied over the entire surface to planarize the substrate surface (step S3). By this SOG application, the concave portions between the wiring patterns on the substrate are filled with SOG4 and the unevenness of the wiring 2 on the substrate is relaxed. This state is shown in FIG.

Next, the SOG4 is entirely etched back to achieve the first smoothing (step S4). The etching conditions at this time are as follows:
The SOG / oxide insulating film is set in the range of 0.7 to 1.3, preferably about 1. As a result, the surface is substantially flattened, leaving the SOG in the recesses between the wirings. However, in this state, the SOG is satisfactorily buried in the portion with the narrow wiring interval, but the SOG is etched in the portion with the wide wiring interval to form a large step D. This state is shown in the cross section of FIG. Steps S1 to so far
The first smoothing step is up to S4.

Next, a silicon nitride film (P
-SiN) 5 is formed by plasma CVD (step S5). The thickness of this silicon nitride film 5 is S
The thickness is made larger than the maximum step D generated by the OG etch back. In this case, since the SOG etch-back fills the recesses between the wirings with SOG to some extent, the occurrence of voids that are likely to occur particularly in the narrow recesses is suppressed. This void is generated because the inlet portion is closed due to the overhang of the inlet portion of the concave portion and a space is formed inside.

Next, a resist 6 is applied on the entire surface of the silicon nitride film 5 to flatten the surface (step S6).
This state is shown in FIG.

Next, the resist 6 is entirely etched back to achieve the second smoothing (step S7). The etching conditions at this time are set so that the selection ratio with respect to the underlying silicon nitride film 5 and the resist / P-SiN are in the range of 0.7 to 1.3, preferably about 1. Also,
Etching gas is SF6 / O2 binary system or CF4
A ternary system of / CHF3 / Ar is used. Further, in this case, the etching rate for the oxide insulating film 3 which is the base of the silicon nitride film 5 is sufficiently slow and has sufficient selectivity with respect to the resist etch back, so that the oxide insulating film 3 is hardly etched in overetching. To set. As a result, it is possible to prevent the interlayer insulating film from being excessively removed by etching back twice, and to secure a necessary thickness of the interlayer insulating film.

By the resist etching back in the second step, the recesses left in the SOG etching back in the first step are almost completely filled with P-SiN and the surface smoothing is achieved. This state is shown in FIG.

Next, in step S8, an oxide film or a silicon nitride film (P-
SiN) is grown by CVD to form an interlayer insulating film 7 having a desired thickness.
Get. This state is shown in FIG. Thereafter, an upper aluminum wiring (not shown) is formed on this interlayer insulating film 7 (step S9).

In the second embodiment of the smoothing process in the above embodiment, the resist is used for etching back, but it is easy to set the etching selection ratio to the underlying P-SiN to about 1. Then, another flattening coating material (for example, SOG) can be used. Also,
In this case, an insulating film other than P-SiN may be used as the base insulating film.

[0032]

As described above, according to the present invention, the SO
When the first smoothing process using G sufficiently smoothes the portion having a narrow wiring interval and a step is formed in the portion having a wide wiring interval, the second smoothing step causes the step portion to be smoothed. Is sufficiently smoothed by an etch-back process using a resist or the like, and the interlayer insulating film as a whole is planarized regardless of the layout of the wiring pattern and the width of the wiring. As a result, the coverage of the wiring can be improved, a stable wiring layer having desired characteristics can be obtained, and the reliability of the wiring can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

2A, 2B, and 2C are cross-sectional views of the substrate, which sequentially show different steps of the flow of FIG.

3 (D), (E), and (F) are cross-sectional views of the substrate, respectively showing steps following the step shown in FIG. 2 in order.

FIG. 4 is a flowchart of a conventional semiconductor device manufacturing method.

5A, 5B, and 5C are cross-sectional views of the substrate, showing the respective steps of the flow of FIG. 4 in order.

[Explanation of symbols]

1: silicon substrate, 2: aluminum wiring, 3: oxide insulating film,
4: SOG, 5: silicon nitride film, 6: resist.

Claims (7)

[Claims] 1. A first smoothing step for smoothing an interlayer insulating film between wiring layers and a second smoothing step following the first smoothing step, wherein the first smoothing step comprises: (a) a lower layer on the substrate. Forming a wiring; (b) forming a first insulating film on the lower wiring; (c) applying SOG on the first insulating film; and (d) etching back the SOG. The second smoothing step comprises: (e) forming a second insulating film on the substrate surface after the SOG etch back; and (f) forming a second insulating film on the second insulating film. Applying a flattening coating material; (g) etching back the flattening coating material; and (h) forming an interlayer insulating film on the substrate surface after the flattening coating material is etched back. And (i) on the interlayer insulating film The method of manufacturing a semiconductor device characterized by comprising a step of forming the upper wiring. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film in the first smoothing step is made of an oxide film-based insulating material containing Si. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film in the second smoothing step is made of a Si nitride film. 4. The flattening coating material in the second smoothing step comprises a resist.
A method of manufacturing a semiconductor device according to item 1. 5. The second insulating film in the second smoothing step,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness is formed to be equal to or larger than a film thickness corresponding to a maximum step difference that occurs after SOG etch back. 6. The SOG etchback in the first smoothing step is performed under the condition that the etching selection ratio of SOG / underlying insulating film is about 0.7 to 1.3.
A method of manufacturing a semiconductor device according to item 1. 7. The etching back of the flattening coating material in the second smoothing step is performed under the condition that the flattening coating material / base insulating film etching selection ratio is about 0.7 to 1.3. The method for manufacturing a semiconductor device according to claim 1, further comprising: