JPH0794509A - Semiconductor element and its manufacture - Google Patents

Abstract

PURPOSE:To produce a high-reliability semiconductor element capable of preventing disconnection and short-circuits which cause defective characteristicss in multilayer interconnection by depositing a flat layer insulating film. CONSTITUTION:After forming a first wiring pattern 22 on a substrate 21 and forming an ARM film 23 on the first wiring pattern 22, a flat layer insulating film comprising a plasma oxide film 24, an ozone TEOS.NSG film 25 and plasma oxide film 26 is deposited. And a second wiring pattern 28 is formed on the layer insulating film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an interlayer insulating film between wirings is flattened in a multilayer wiring process in order to prevent a disconnection and a short circuit, which are the causes of characteristic defects in the multilayer wiring, and a method for manufacturing the same. It is about.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Reference: Japanese Patent Application Laid-Open No. 4-167429. The reference describes a spin-on-glass (hereinafter referred to as SOG) technique for forming a flat interlayer insulating film. 2 (a) to (d),
It is a manufacturing process drawing of a conventional semiconductor device such as a MOS transistor using the SOG technology. Hereinafter, the manufacturing steps (1) to (4) will be described with reference to FIGS. (1) Step of FIG. 2A A wiring material made of metal is formed on the substrate 1 and selectively etched by using a photolithography technique to form a first
After forming the wiring pattern 2 of, the vapor phase growth method (Chemical
Vapor Deposition method (hereinafter referred to as the CVD method)
Non-doped silicate glass (Nondoped SilicateGlass), which is an oxide film without impurities,
Phosphosilicate glass (NSG) and an oxide film mixed with phosphorus as an impurity
An oxide film 3 such as ass (hereinafter referred to as PSG) is formed on the entire surface. The CVD method is a method of depositing a thin film on a substrate at a high temperature of, for example, about 750 to 800 ° C. by utilizing thermal decomposition or chemical reaction in a gas phase. (2) Step of FIG. 2 (b) A silica-based coating liquid containing silanol as a main component is applied to the entire surface of the substrate 1, and the SOG film 4 is coated and cured. (3) Step of FIG. 2C The CVD method is used again to form an oxide film 5 of NSG, PSG or the like on the entire surface. (4) Process of FIG. 2D: Oxide film 3, oxide film 4, and oxide film 5 on the metal wiring 1.
A through hole 5a is formed by opening an interlayer insulating film made of. Next, a wiring material made of metal is formed on the oxide film 5 and selectively etched by using a photolithography technique to form a second metal wiring pattern 6.

FIGS. 3A to 3D are manufacturing process diagrams of another conventional semiconductor element such as a MOS transistor using the etchback technique. Hereinafter, the manufacturing process (1)-
(4) will be described with reference to FIGS. (1) Step of FIG. 3A A wiring material made of metal is formed on the substrate 11 and selectively etched using a photolithography technique to form a first wiring pattern 12, and then a CVD method is used. Is used to form an oxide film 13 of NSG, PSG or the like on the entire surface. (2) Step of FIG. 3 (b) A resist or SOG film to be the sacrificial film 14 is coated and cured on the entire surface of the substrate. (3) Step of FIG. 3C Using a dry etching method, the entire surface of the substrate is etched under the etching condition that the oxide film 13 and the sacrificial film 14 have substantially the same etching rate. (4) Step of FIG. 3D The oxide film 15 is formed again by using the CVD method, and the oxide film 13a on the metal wiring 12 and the interlayer insulating film made of the oxide film 15 are opened to form the through hole 15a. Form. Next, a wiring material made of metal is formed on the oxide film 15 and selectively etched by using a photolithography technique to form a second
The metal wiring pattern 16 is formed.

[0004]

However, the semiconductor device having the above structure and the method for manufacturing the same have the following problems. (A) In the SOG technique, the planarization of the interlayer insulating film is insufficient, and the reliability of the second wiring pattern 6 that crosses the upper portion of the first wiring pattern 2 becomes low. (B) In the above-mentioned etch-back technique, it is necessary to form the oxide film 13 on the base in order to completely remove the sacrificial film 14. However, when the wiring gap is 1 micron or less, a void is generated in the oxide film 13. Therefore, disconnection or short circuit is likely to occur, and the reliability of the second wiring pattern 16 becomes low. The present invention has solved the problems that the prior art has, such as generation of voids in an oxide film, and insufficient flattening of the oxide film, and a semiconductor element having high wiring reliability and the same. A manufacturing method is provided.

[0005]

In order to solve the above-mentioned problems, a first invention includes a first wiring pattern arranged on a substrate having an element region formed thereon and electrically connected to the element region. In a semiconductor device including an interlayer insulating film deposited on the first wiring pattern and a second wiring pattern formed on the interlayer insulating film, the interlayer insulating film is configured as follows. is doing. That is, the interlayer insulating film is formed on the first oxide film so as to fill the first oxide film deposited on the entire surface of the substrate and the slit portion having a predetermined width or less on the surface of the first oxide film. A second oxide film made of deposited tetraethylorthosilicate (hereinafter referred to as TEOS) / NSG, and a third oxide film deposited on the second oxide film and having a flatly etched surface are formed. There is. In the second invention, a first wiring pattern is selectively formed on a substrate, an interlayer insulating film is deposited on the first wiring pattern, and then a second wiring pattern is selected on the interlayer insulating film. In the method of manufacturing a semiconductor element to be formed in a specific manner, the interlayer insulating film is formed as follows. That is, the interlayer insulating film is formed by using a first step of depositing a first oxide film on the entire surface of the substrate by using a plasma CVD method after forming an antireflection film on the first wiring pattern, and using an ozone gas. The second step of depositing a second oxide film made of TEOS.NSG on the first oxide film by the conventional CVD method, and a third oxide film on the second oxide film by the plasma CVD method. And a third sacrificial film is formed on the third oxide film, and the third oxide film and the sacrificial film are etched under substantially the same etching rate. A sacrificial film and the third oxide film are entirely etched to planarize the third oxide film to form a fourth step, which is sequentially formed. In the third invention, the first oxide film of the second invention is 2000 to 4000 Å, and the second oxide film is 20
00-4000Å, the third oxide film is 1.0-1.
The film is formed to have a film thickness of 5 μm.

[0006]

According to the first aspect of the invention, since the semiconductor element is configured as described above, the first oxide film is adhered to the substrate and the second oxide film formed on the first oxide film. It works to improve strength. The second oxide film functions to suppress the generation of voids. Further, the third oxide film has a function of flattening the bottom of the second wiring pattern formed on the third oxide film and suppressing disconnection or short circuit which occurs in the second wiring pattern. In the manufacturing method of the second invention, the plasma CVD method for forming the first oxide film produces a strong oxide film which is superior in stain resistance and moisture resistance as compared with the oxide film formed by the CVD method. It has a function. The CVD method using ozone gas for forming the second oxide film has a function of forming a flat oxide film without voids. Plasma C forming a third oxide film
Similar to the case of the first oxide film, the VD method has a function of generating a strong oxide film having excellent stain resistance and moisture resistance as compared with the oxide film formed by the CVD method. Further, the overall etching performed after forming the flat sacrificial film on the third oxide film has a function of eliminating the unevenness on the surface of the interlayer insulating film under the second wiring pattern. According to the third invention, the first oxide film functions to improve the adhesion strength between the substrate and the second oxide film. The second oxide film functions to fill the gap between the wiring patterns without generating voids. Furthermore, the third
The oxide film has a function of preventing insulation deterioration of the underlayer.
Therefore, the above problem can be solved.

[0007]

First Embodiment FIG. 1 is a vertical sectional view of a semiconductor device showing a first embodiment of the present invention. This semiconductor element has, for example, a substrate 21 made of silicon in which a drain and a source of a MOS transistor are formed. Al on the substrate 21
A first wiring pattern 22 made of a metal such as Al is formed, and an anti-reflection film (hereinafter referred to as an ARM film) is further formed on the first wiring pattern 22.
23 is formed. In addition, a plasma oxide film 24 which is a first oxide film and an ozone T which is a second oxide film are formed on the entire surface.
A flat interlayer insulating film composed of the EOS / NSG film 25 and the plasma oxide film 26 which is the third oxide film is deposited. A second wiring pattern 28 made of a metal such as Al is formed on the interlayer insulating film. In the semiconductor element configured as described above, when a current flows through the first and second wiring patterns, the source and drain formed in the substrate perform a predetermined operation. In the present embodiment, since the interlayer insulating film is flat at the intersection of the first wiring pattern 22 and the second wiring pattern 28 without any constriction,
It is possible to prevent the disconnection and the short circuit which are the causes of the characteristic failure in the multilayer wiring.

Second Embodiment FIGS. 4 (a) to 4 (d) are manufacturing process diagrams showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention. Each step (a) will be described below. (D) will be described. (1) Step of FIG. 4 (a) A wiring material made of metal is formed on the substrate 21, an ARM film for preventing light reflection is formed on the wiring material, and then selectively etched by using a photolithography technique. And then the first
The wiring pattern 22 and the ARM film 23 are formed. After that, a plasma oxide film 24, which is a first oxide film, is formed on the entire surface of the substrate by using the plasma CVD method. Plasma CVD
The method is, for example, applying a high frequency electric field to the reaction gas and activating the gas by utilizing the electric energy of the reaction gas.
At a reduced pressure of about r, 30
This is a method of forming a thin film on the substrate surface at a low temperature of around 0 ° C. The plasma oxide film formed by the plasma CVD method is CVD
Compared with the oxide film formed by the method, it is excellent in stain resistance and moisture resistance and is effective as a protective film. (2) Process of FIG. 4B The ozone TEOS / NSG film 25, which is the second oxide film, is formed on the entire surface by using the atmospheric pressure (760 Torr) ozone CVD method capable of forming a flat oxide film without voids. To form. Thickness of plasma oxide film 24 and ozone TEOSN
By selecting the film thickness of the SG film 25, the ozone TEOS / NSG film 25 is embedded in the wiring slit portion 22a having an aspect ratio (metal wiring thickness / wiring slit width) of up to about 1.4 without generating voids. It can be formed.

(3) Step of FIG. 4 (c) The plasma oxide film 26a, which is a third oxide film having a film thickness of 1.0 to 1.5 μm, is formed by ozone T using the plasma CVD method.
It is formed on the entire surface of the EOS / NSG film 25. Further, the entire surface of the plasma oxide film 26a is coated and cured with a resist or an SOG film in a thickness of 0.8 to 1.0 μm,
The sacrificial film 27 is formed. (4) Step of FIG. 4 (d) Tetrafluoromethane (CF ₄ ), Trifluoromethane (C
The surface of the plasma oxide film 26a is, for example, 1.8 to 2.0 μm by dry etching using a gas such as HF ₃ ).
The entire surface is etched to form a flat plasma oxide film 26. Further, similarly to the first wiring pattern, a second wiring pattern 28 made of a metal such as Al is selectively formed on the plasma oxide film 26 by the photolithography technique. As described above, in this embodiment, since the plasma oxide film 24, the ozone TEOS / NSG film 25, and the plasma oxide film 26 are deposited in this order, no void is generated in the wiring gap of 1.0 μm or less, A flat interlayer insulating film can be formed. Therefore, it is possible to manufacture a highly reliable semiconductor element in which the disconnection and the short circuit which are the causes of the characteristic failure in the multilayer wiring are prevented. In addition,
The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (A) The material, shape, and structure of the semiconductor element of the embodiment of the present invention may be other materials, shapes, and structures. (B) As the plasma CVD method, an ECR (Electron Cyclotron Resonance) plasma CVD method capable of depositing an oxide film at room temperature may be used. (C) TEOS is tetramethyl orthosilicate (T
MOS), tetrapropyl orthosilicate (TPO
Even if S) is used, almost the same operation and effect as those of the above-mentioned embodiment can be obtained. (D) The wiring pattern of the embodiment of the present invention may have three or more layers.

[0010]

As described in detail above, according to the semiconductor element of the first invention, the interlayer insulating film is flat without any constriction at the intersection of the first wiring pattern and the second wiring pattern. Therefore, it is possible to provide a highly reliable semiconductor element in which disconnection and short circuit, which are the causes of characteristic defects in multilayer wiring, are prevented. According to the manufacturing method of the second invention, since the first plasma oxide film is formed by using the plasma CVD method, it is excellent in stain resistance and moisture resistance as compared with the oxide film formed by the CVD method. Further, ozone TE is formed on the first plasma oxide film by the atmospheric pressure ozone CVD method.
Since the OS / NSG film 25 is formed on the entire surface, it is possible to form a flat oxide film without voids. Further, after forming the second plasma oxide film on the entire surface of the ozone TEOS / NSG film 25 by using the plasma CVD method, the sacrificial film is coated and cured on the entire surface of the second plasma oxide film to further flatten the surface. Therefore, the second plasma oxide film having a flat surface can be formed by etching the entire surface.
Since the second wiring pattern is formed on the second plasma oxide film, it is possible to manufacture a highly reliable semiconductor element in which the disconnection and the short circuit which are the causes of the characteristic failure in the multilayer wiring are prevented. According to the third invention, the film thickness of the first oxide film is effective for improving the adhesion strength between the substrate and the second oxide film. The film thickness of the second oxide film is suitable for filling the gap between the wiring patterns without generating voids. The film thickness of the third oxide film is appropriate for preventing insulation deterioration of the underlayer.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view of a semiconductor device showing a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram showing a conventional method of manufacturing a semiconductor device.

FIG. 3 is a manufacturing process diagram illustrating another conventional method for manufacturing a semiconductor element.

FIG. 4 is a manufacturing process diagram showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

[Explanation of symbols]

 21 Substrate 22, 28 Wiring Pattern 23 ARM Film 24, 26 Oxide Film 25 Ozone TEOS / NSG Film 27 Sacrificial Film

Claims (3)

[Claims] 1. A first wiring pattern disposed on a substrate having an element region formed therein and electrically connected to the element region; an interlayer insulating film deposited on the first wiring pattern; In a semiconductor device including a second wiring pattern formed on an interlayer insulating film, the interlayer insulating film includes a first oxide film deposited on the entire surface of the substrate, and the first oxide film. Tetraethyl orthosilicate non-doped silicate deposited on the first oxide film so as to fill the slit portion having a predetermined width or less on the surface.
A semiconductor element comprising a second oxide film made of glass and a third oxide film deposited on the second oxide film and having a flatly etched surface. 2. A first wiring pattern is selectively formed on a substrate, an interlayer insulating film is deposited on the first wiring pattern, and then a second wiring pattern is selectively formed on the interlayer insulating film. In the method of manufacturing a semiconductor element formed in step 1, the interlayer insulating film is formed by coating a first oxide film on the entire surface of the substrate by plasma vapor deposition after forming an antireflection film on the first wiring pattern. And a second step of depositing a second oxide film of tetraethylorthosilicate non-doped silicate glass on the first oxide film by a vapor phase growth method using ozone gas, A third step of depositing a third oxide film on the second oxide film using a plasma vapor deposition method, and forming a flat sacrificial film on the third oxide film, Etching between the oxide film and the sacrificial film The bets are planarized oxide film of the third and entirely etching the sacrificial film and the oxide film of the third at substantially equal become etching condition 4
The method of manufacturing a semiconductor element, the method including: 3. The first oxide layer has a thickness of about 2000-400.
3. The method for manufacturing a semiconductor device according to claim 2, wherein the second oxide film is formed to a thickness of about 2000 to 4000 and the third oxide film is formed to a thickness of about 1.0 to 1.5 .mu.m. .