JPH0218640A - マイクロコンピユータ・システム - Google Patents

マイクロコンピユータ・システム

Info

Publication number
JPH0218640A
JPH0218640A JP1117621A JP11762189A JPH0218640A JP H0218640 A JPH0218640 A JP H0218640A JP 1117621 A JP1117621 A JP 1117621A JP 11762189 A JP11762189 A JP 11762189A JP H0218640 A JPH0218640 A JP H0218640A
Authority
JP
Japan
Prior art keywords
bus
address
signal
cpu
posted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1117621A
Other languages
English (en)
Japanese (ja)
Inventor
Ralph M Begun
ラルフ・マライ・ビイガン
Patrick M Bland
パトリツク・モーリス・ブランド
Mark E Dean
マーク・エドワード・デイーン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH0218640A publication Critical patent/JPH0218640A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Microcomputers (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
  • Hardware Redundancy (AREA)
  • Peptides Or Proteins (AREA)
  • Medicines Containing Material From Animals Or Micro-Organisms (AREA)
  • Information Transfer Systems (AREA)
  • Compositions Of Macromolecular Compounds (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Bus Control (AREA)
  • Mobile Radio Communication Systems (AREA)
JP1117621A 1988-05-26 1989-05-12 マイクロコンピユータ・システム Pending JPH0218640A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US19889388A 1988-05-26 1988-05-26
US198893 1988-05-26

Publications (1)

Publication Number Publication Date
JPH0218640A true JPH0218640A (ja) 1990-01-22

Family

ID=22735311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1117621A Pending JPH0218640A (ja) 1988-05-26 1989-05-12 マイクロコンピユータ・システム

Country Status (24)

Country Link
EP (1) EP0343768B1 (https=)
JP (1) JPH0218640A (https=)
KR (1) KR930001585B1 (https=)
CN (1) CN1019153B (https=)
AT (1) ATE125051T1 (https=)
AU (1) AU611288B2 (https=)
BE (1) BE1002652A4 (https=)
BR (1) BR8902381A (https=)
CA (1) CA1314330C (https=)
DE (2) DE68923402T2 (https=)
DK (1) DK189789A (https=)
ES (1) ES2075044T3 (https=)
FI (1) FI891785A7 (https=)
FR (1) FR2632095A1 (https=)
GB (1) GB2219107A (https=)
HK (1) HK23796A (https=)
IT (1) IT1230190B (https=)
MX (1) MX171667B (https=)
MY (1) MY108557A (https=)
NL (1) NL8901255A (https=)
NO (1) NO174984C (https=)
NZ (1) NZ228784A (https=)
PT (1) PT90632B (https=)
SE (1) SE8901305L (https=)

Also Published As

Publication number Publication date
CN1040875A (zh) 1990-03-28
KR930001585B1 (ko) 1993-03-05
CA1314330C (en) 1993-03-09
IT8920625A0 (it) 1989-05-24
DE3909909C2 (https=) 1990-05-31
PT90632B (pt) 1995-12-29
AU3409889A (en) 1989-11-30
DK189789A (da) 1989-11-27
IT1230190B (it) 1991-10-18
MY108557A (en) 1996-10-31
NO891582L (no) 1989-11-27
DE68923402T2 (de) 1996-03-07
SE8901305D0 (sv) 1989-04-11
MX171667B (es) 1993-11-10
BE1002652A4 (fr) 1991-04-23
FI891785A7 (fi) 1989-11-27
DK189789D0 (da) 1989-04-19
EP0343768B1 (en) 1995-07-12
AU611288B2 (en) 1991-06-06
NZ228784A (en) 1991-04-26
EP0343768A2 (en) 1989-11-29
EP0343768A3 (en) 1991-03-20
DE68923402D1 (de) 1995-08-17
GB8904918D0 (en) 1989-04-12
HK23796A (en) 1996-02-16
ES2075044T3 (es) 1995-10-01
DE3909909A1 (de) 1989-11-30
NO174984B (no) 1994-05-02
GB2219107A (en) 1989-11-29
FI891785A0 (fi) 1989-04-14
CN1019153B (zh) 1992-11-18
KR890017614A (ko) 1989-12-16
NL8901255A (nl) 1989-12-18
NO891582D0 (no) 1989-04-18
NO174984C (no) 1994-08-10
ATE125051T1 (de) 1995-07-15
FR2632095A1 (fr) 1989-12-01
SE8901305L (sv) 1989-11-27
BR8902381A (pt) 1990-01-16
PT90632A (pt) 1989-11-30

Similar Documents

Publication Publication Date Title
JP2571673B2 (ja) 多重化バスを有する情報処理システムでバック・ツー・バック・データ転送を提供する方法および装置
US5045998A (en) Method and apparatus for selectively posting write cycles using the 82385 cache controller
US6405271B1 (en) Data flow control mechanism for a bus supporting two-and three-agent transactions
US5524235A (en) System for arbitrating access to memory with dynamic priority assignment
US5301279A (en) Apparatus for conditioning priority arbitration
US5919254A (en) Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
US5528764A (en) Bus system with cache snooping signals having a turnaround time between agents driving the bus for keeping the bus from floating for an extended period
US6598103B2 (en) Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system
EP0427425B1 (en) Improved paged memory controller
JPH0623960B2 (ja) マイクロコンピユータ・システム
US5678064A (en) Local bus-ISA bridge for supporting PIO and third party DMA data transfers to IDE drives
KR19990029295A (ko) 가변폭 버스의 동시적인 액세스를 이용하는 다중프로세서시스템에서 ｉ/ｏ 제어를 위한 방법 및 시스템
US5327545A (en) Data processing apparatus for selectively posting write cycles using the 82385 cache controller
US7007126B2 (en) Accessing a primary bus messaging unit from a secondary bus through a PCI bridge
AU615542B2 (en) Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385
US5923857A (en) Method and apparatus for ordering writeback data transfers on a bus
US5097483A (en) Tri-statable bus with apparatus to drive bus line to first level and then second level for predetermined time before turning off
US6327636B1 (en) Ordering for pipelined read transfers
US5809534A (en) Performing a write cycle to memory in a multi-processor system
JPH0218640A (ja) マイクロコンピユータ・システム
EP0661641A2 (en) A computer system
CN1195141A (zh) 用于实现高速缓冲存储器流式存取的方法和设备
US5423021A (en) Auxiliary control signal decode using high performance address lines
KR100268178B1 (ko) 캐쉬 기능을 가지는 피시아이 장치
EP0661640A1 (en) System and method for accessing data in a computer system including a cache controller and a memory controller connected in parallel