JPH02147928U - - Google Patents
Info
- Publication number
- JPH02147928U JPH02147928U JP5726589U JP5726589U JPH02147928U JP H02147928 U JPH02147928 U JP H02147928U JP 5726589 U JP5726589 U JP 5726589U JP 5726589 U JP5726589 U JP 5726589U JP H02147928 U JPH02147928 U JP H02147928U
- Authority
- JP
- Japan
- Prior art keywords
- metal case
- elements
- filter package
- circuit board
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000005476 soldering Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
- Casings For Electric Apparatus (AREA)
- Filters And Equalizers (AREA)
Description
第1図a及びbは本考案の第1の実施例の概略
構成説明図及び一部拡大説明図、第2図は本考案
の第2の実施例の構成説明図、第3図は一般的な
バンド・パス・フイルタの回路図、第4図はパツ
ケージ化したフイルタの構成説明図である。
30……プリント基板、32,33……チツプ
部品化された素子、35……周縁部のアースパタ
ーン、40……各接続用電極、41……配線パタ
ーン、43……アース用電極、45……アースパ
ターン、50……ハンダ、55……金属ケース。
Figures 1a and b are schematic structural explanatory diagrams and partially enlarged explanatory diagrams of the first embodiment of the present invention, Figure 2 is a structural explanatory diagram of the second embodiment of the present invention, and Figure 3 is a general diagram. FIG. 4 is an explanatory diagram of the configuration of a packaged filter. 30...Printed circuit board, 32, 33...Element made into chip component, 35...Grounding pattern on the periphery, 40...Each connection electrode, 41...Wiring pattern, 43...Earth electrode, 45... ...Earth pattern, 50...Solder, 55...Metal case.
Claims (1)
たプリント基板と、金属ケースとを有したフイル
タ・パツケージにおいて、前記各素子をチツプ部
品にするとともに、プリント基板周縁部に環状に
形成したアースパターンを該金属ケースとハンダ
接続し、更に各素子のアース電極を該周縁部アー
スパターン或は該金属ケースと接地したことを特
徴とするフイルタ・パツケージの構造。 In a filter package that has a printed circuit board on which L/C circuit elements, piezoelectric filter elements, etc. are mounted, and a metal case, each of the elements is made into a chip component, and an annular ground pattern is formed on the periphery of the printed circuit board. A structure of a filter package characterized in that the filter package is connected to the metal case by soldering, and further, the ground electrode of each element is grounded to the peripheral earth pattern or the metal case.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5726589U JPH02147928U (en) | 1989-05-18 | 1989-05-18 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5726589U JPH02147928U (en) | 1989-05-18 | 1989-05-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02147928U true JPH02147928U (en) | 1990-12-17 |
Family
ID=31581820
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5726589U Pending JPH02147928U (en) | 1989-05-18 | 1989-05-18 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02147928U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0480125U (en) * | 1990-11-27 | 1992-07-13 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60236283A (en) * | 1984-05-10 | 1985-11-25 | ロ−ム株式会社 | Electronic circuit board |
JPS6338400B2 (en) * | 1985-06-04 | 1988-07-29 | Kunyoshi Kawakita | |
JPS63296299A (en) * | 1987-05-27 | 1988-12-02 | Nec Corp | Hybrid integrated circuit device |
-
1989
- 1989-05-18 JP JP5726589U patent/JPH02147928U/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60236283A (en) * | 1984-05-10 | 1985-11-25 | ロ−ム株式会社 | Electronic circuit board |
JPS6338400B2 (en) * | 1985-06-04 | 1988-07-29 | Kunyoshi Kawakita | |
JPS63296299A (en) * | 1987-05-27 | 1988-12-02 | Nec Corp | Hybrid integrated circuit device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0480125U (en) * | 1990-11-27 | 1992-07-13 |