JPH021371B2 - - Google Patents

Info

Publication number
JPH021371B2
JPH021371B2 JP57133928A JP13392882A JPH021371B2 JP H021371 B2 JPH021371 B2 JP H021371B2 JP 57133928 A JP57133928 A JP 57133928A JP 13392882 A JP13392882 A JP 13392882A JP H021371 B2 JPH021371 B2 JP H021371B2
Authority
JP
Japan
Prior art keywords
lsi
film carrier
film
positioning
carrier lsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57133928A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5923555A (ja
Inventor
Masayuki Higuchi
Masahiro Higami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP13392882A priority Critical patent/JPS5923555A/ja
Publication of JPS5923555A publication Critical patent/JPS5923555A/ja
Publication of JPH021371B2 publication Critical patent/JPH021371B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
JP13392882A 1982-07-30 1982-07-30 フイルム・キヤリヤｌｓｉの実装方法 Granted JPS5923555A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13392882A JPS5923555A (ja) 1982-07-30 1982-07-30 フイルム・キヤリヤｌｓｉの実装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13392882A JPS5923555A (ja) 1982-07-30 1982-07-30 フイルム・キヤリヤｌｓｉの実装方法

Publications (2)

Publication Number Publication Date
JPS5923555A JPS5923555A (ja) 1984-02-07
JPH021371B2 true JPH021371B2 (ko) 1990-01-11

Family

ID=15116351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13392882A Granted JPS5923555A (ja) 1982-07-30 1982-07-30 フイルム・キヤリヤｌｓｉの実装方法

Country Status (1)

Country Link
JP (1) JPS5923555A (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750724B2 (ja) * 1986-12-17 1995-05-31 株式会社日立製作所 液晶表示装置
JP2812627B2 (ja) * 1992-10-30 1998-10-22 三菱電機株式会社 テープキャリア、半導体装置試験方法及び装置
JP2509804B2 (ja) * 1994-07-22 1996-06-26 シャープ株式会社 表示装置
JP2002093861A (ja) * 2000-09-12 2002-03-29 Mitsui Mining & Smelting Co Ltd ２メタルｔａｂ及び両面ｃｓｐ、ｂｇａテープ、並びにその製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4983382A (ko) * 1972-11-18 1974-08-10
JPS544375A (en) * 1977-06-13 1979-01-13 Suwa Seikosha Kk Circuit substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4983382A (ko) * 1972-11-18 1974-08-10
JPS544375A (en) * 1977-06-13 1979-01-13 Suwa Seikosha Kk Circuit substrate

Also Published As

Publication number Publication date
JPS5923555A (ja) 1984-02-07

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