JPH02135763A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH02135763A
JPH02135763A JP63290780A JP29078088A JPH02135763A JP H02135763 A JPH02135763 A JP H02135763A JP 63290780 A JP63290780 A JP 63290780A JP 29078088 A JP29078088 A JP 29078088A JP H02135763 A JPH02135763 A JP H02135763A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor element
bumps
cap
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63290780A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0583187B2 (enrdf_load_stackoverflow
Inventor
Hiroshi Saito
宏 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP63290780A priority Critical patent/JPH02135763A/ja
Publication of JPH02135763A publication Critical patent/JPH02135763A/ja
Publication of JPH0583187B2 publication Critical patent/JPH0583187B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP63290780A 1988-11-16 1988-11-16 半導体装置 Granted JPH02135763A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63290780A JPH02135763A (ja) 1988-11-16 1988-11-16 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63290780A JPH02135763A (ja) 1988-11-16 1988-11-16 半導体装置

Publications (2)

Publication Number Publication Date
JPH02135763A true JPH02135763A (ja) 1990-05-24
JPH0583187B2 JPH0583187B2 (enrdf_load_stackoverflow) 1993-11-25

Family

ID=17760414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63290780A Granted JPH02135763A (ja) 1988-11-16 1988-11-16 半導体装置

Country Status (1)

Country Link
JP (1) JPH02135763A (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000067315A1 (fr) * 1999-05-03 2000-11-09 Stmicroelectronics S.A. Protection d'une puce semiconductrice
US6294408B1 (en) * 1999-01-06 2001-09-25 International Business Machines Corporation Method for controlling thermal interface gap distance
JP2017059774A (ja) * 2015-09-18 2017-03-23 セイコーインスツル株式会社 電子部品
JP2017126645A (ja) * 2016-01-13 2017-07-20 セイコーインスツル株式会社 電子部品

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6294408B1 (en) * 1999-01-06 2001-09-25 International Business Machines Corporation Method for controlling thermal interface gap distance
WO2000067315A1 (fr) * 1999-05-03 2000-11-09 Stmicroelectronics S.A. Protection d'une puce semiconductrice
JP2017059774A (ja) * 2015-09-18 2017-03-23 セイコーインスツル株式会社 電子部品
JP2017126645A (ja) * 2016-01-13 2017-07-20 セイコーインスツル株式会社 電子部品

Also Published As

Publication number Publication date
JPH0583187B2 (enrdf_load_stackoverflow) 1993-11-25

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Legal Events

Date Code Title Description
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