JPH02119164A - 半導体モジユール - Google Patents

半導体モジユール

Info

Publication number
JPH02119164A
JPH02119164A JP1242082A JP24208289A JPH02119164A JP H02119164 A JPH02119164 A JP H02119164A JP 1242082 A JP1242082 A JP 1242082A JP 24208289 A JP24208289 A JP 24208289A JP H02119164 A JPH02119164 A JP H02119164A
Authority
JP
Japan
Prior art keywords
ceramic
circuit board
multilayer circuit
thermal expansion
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1242082A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0544190B2 (enrdf_load_stackoverflow
Inventor
Nobuyuki Ushifusa
信之 牛房
Koichi Shinohara
浩一 篠原
Nobunari Nagayama
永山　更成
Satoru Hagiwara
萩原　覚
Tasao Soga
太佐男 曽我
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1242082A priority Critical patent/JPH02119164A/ja
Publication of JPH02119164A publication Critical patent/JPH02119164A/ja
Publication of JPH0544190B2 publication Critical patent/JPH0544190B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676—Single layer compositions

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP1242082A 1989-09-20 1989-09-20 半導体モジユール Granted JPH02119164A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1242082A JPH02119164A (ja) 1989-09-20 1989-09-20 半導体モジユール

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1242082A JPH02119164A (ja) 1989-09-20 1989-09-20 半導体モジユール

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP61130136A Division JPS62287658A (ja) 1986-06-06 1986-06-06 セラミックス多層回路板

Publications (2)

Publication Number Publication Date
JPH02119164A true JPH02119164A (ja) 1990-05-07
JPH0544190B2 JPH0544190B2 (enrdf_load_stackoverflow) 1993-07-05

Family

ID=17084023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1242082A Granted JPH02119164A (ja) 1989-09-20 1989-09-20 半導体モジユール

Country Status (1)

Country Link
JP (1) JPH02119164A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214006A (en) * 1991-02-05 1993-05-25 Indresco Inc. Cement-free silicon carbide monoliths
JPWO2018168758A1 (ja) * 2017-03-15 2019-03-22 住友ベークライト株式会社 樹脂シート、積層樹脂シート、および樹脂組成物

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55128899A (en) * 1979-03-23 1980-10-06 Ibm Method of fabricating glass ceramic structure
JPS5815264A (ja) * 1981-07-21 1983-01-28 Nec Corp マルチチツプパツケ−ジ
JPS5843553A (ja) * 1981-09-08 1983-03-14 Nec Corp マルチチツプｌｓｉパツケ−ジ
JPS58137294A (ja) * 1982-02-09 1983-08-15 株式会社日立製作所 電気的相互接続パツケ−ジの製造方法
JPS59107596A (ja) * 1982-12-13 1984-06-21 株式会社日立製作所 セラミツク多層配線回路板
JPS6010698A (ja) * 1983-06-29 1985-01-19 日本電気株式会社 多層配線基板およびその製造方法
JPS6027191A (ja) * 1983-07-25 1985-02-12 株式会社日立製作所 ガラスセラミツクス多層配線基板の積層法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55128899A (en) * 1979-03-23 1980-10-06 Ibm Method of fabricating glass ceramic structure
JPS5815264A (ja) * 1981-07-21 1983-01-28 Nec Corp マルチチツプパツケ−ジ
JPS5843553A (ja) * 1981-09-08 1983-03-14 Nec Corp マルチチツプｌｓｉパツケ−ジ
JPS58137294A (ja) * 1982-02-09 1983-08-15 株式会社日立製作所 電気的相互接続パツケ−ジの製造方法
JPS59107596A (ja) * 1982-12-13 1984-06-21 株式会社日立製作所 セラミツク多層配線回路板
JPS6010698A (ja) * 1983-06-29 1985-01-19 日本電気株式会社 多層配線基板およびその製造方法
JPS6027191A (ja) * 1983-07-25 1985-02-12 株式会社日立製作所 ガラスセラミツクス多層配線基板の積層法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214006A (en) * 1991-02-05 1993-05-25 Indresco Inc. Cement-free silicon carbide monoliths
JPWO2018168758A1 (ja) * 2017-03-15 2019-03-22 住友ベークライト株式会社 樹脂シート、積層樹脂シート、および樹脂組成物

Also Published As

Publication number Publication date
JPH0544190B2 (enrdf_load_stackoverflow) 1993-07-05

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