JPH02113443U - - Google Patents

Description

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of one embodiment showing the main structure of the present invention, Fig. 2 is a waveform diagram for explaining the operation of the embodiment shown in Fig. 1, and Fig. 3 is a reference voltage FIG. 4 is a waveform diagram showing the operating waveforms when the potential difference between the comparator and the input voltage is small and the frequency of the clock signal is high. FIG. Figure 5 is a configuration diagram showing the configuration of a conventional comparator.
FIG. 6 is a waveform diagram explaining the operation of the circuit shown in FIG. 5, FIG. 7 is a waveform diagram showing the relationship between the logic output and the clock signal when the potential difference between the signal voltage and the reference voltage is small, and FIG. FIG. 6 is a waveform diagram for explaining a problem with the comparator shown in FIG. 5. FIG. AMP...Differential amplifier, CMH, CMH ₁ , C
_MH2 , _CMH3 , CMHN...Comparison/holding circuit, BUF...Buffer circuit, Vi...Input voltage,
Vr...Reference voltage, CLK, <CLK>...Clock signal, Tc...Signal comparison period, TH...Extended holding period.

Claims (1)

[Scope of utility model registration request] In an analog/digital converter that applies multiple reference voltages, compares these reference voltages with an analog input voltage, and outputs the comparison result to a decoder to convert it into a digital signal, the difference is calculated using clock signals that are in opposite phases to each other. The input voltage and the reference voltage are compared in one phase by switching a dynamic switch, and in the other phase, the comparison result is held and expanded to output a logic output. A plurality of comparators are connected in series and synchronized with the clock signal. An analog/digital converter characterized in that the logic level of the logic output is expanded to a predetermined level.