JPH0425331U - - Google Patents
Info
- Publication number
- JPH0425331U JPH0425331U JP6692790U JP6692790U JPH0425331U JP H0425331 U JPH0425331 U JP H0425331U JP 6692790 U JP6692790 U JP 6692790U JP 6692790 U JP6692790 U JP 6692790U JP H0425331 U JPH0425331 U JP H0425331U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- integrator
- reference voltage
- measured
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第1図は本考案の一実施例のブロツク図、第2
図は本実施例における積分器の出力電圧波形図、
第3図は従来のアナログデジタルコンバータのブ
ロツク図、第4図は従来例の積分器の出力電圧波
形図である。
1,13……スイツチ、2,14……積分器、
11……被測定電圧、12……基準電圧発生回路
、15……コンパレータ、16……制御ロジツク
回路、17……カウンタ、18……出力コード。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure shows the output voltage waveform diagram of the integrator in this example.
FIG. 3 is a block diagram of a conventional analog-to-digital converter, and FIG. 4 is an output voltage waveform diagram of a conventional integrator. 1, 13... switch, 2, 14... integrator,
11... Voltage to be measured, 12... Reference voltage generation circuit, 15... Comparator, 16... Control logic circuit, 17... Counter, 18... Output code.
Claims (1)
、前記基準電圧を積分する第1の積分器と、被測
定電圧を積分する第2の積分器と、前記第1およ
び第2の積分器の出力電圧を比較するコンパレー
タと、前記コンパレータの制御によりデジタル量
に変換するカウンタと、アナログデジタル変換の
開始、終了を制御する制御ロジツク回路と、前記
制御ロジツク回路の制御信号により、前記基準電
圧の前記第1の積分器への供給を接又は断とする
第1のスイツチと、前記制御ロジツク回路の同じ
制御信号により、前記被測定電圧の前記第2の積
分器への供給を断又は接とする第2のスイツチと
を有することを特徴とするアナログデジタルコン
バータ。 a reference voltage generation circuit that outputs a constant reference voltage; a first integrator that integrates the reference voltage; a second integrator that integrates the voltage to be measured; and outputs of the first and second integrators. A comparator that compares voltages, a counter that converts the voltage into a digital quantity under the control of the comparator, a control logic circuit that controls the start and end of analog-to-digital conversion, and a control signal of the control logic circuit that converts the reference voltage into a digital quantity. A first switch that connects or disconnects the supply of the voltage to be measured to the second integrator, and a second switch that connects or disconnects the supply of the voltage to be measured to the second integrator by the same control signal of the control logic circuit. An analog-to-digital converter characterized by having two switches.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6692790U JPH0425331U (en) | 1990-06-25 | 1990-06-25 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6692790U JPH0425331U (en) | 1990-06-25 | 1990-06-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0425331U true JPH0425331U (en) | 1992-02-28 |
Family
ID=31600054
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6692790U Pending JPH0425331U (en) | 1990-06-25 | 1990-06-25 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0425331U (en) |
-
1990
- 1990-06-25 JP JP6692790U patent/JPH0425331U/ja active Pending