JPH0198235A - 半導体装置の実装方法 - Google Patents

半導体装置の実装方法

Info

Publication number
JPH0198235A
JPH0198235A JP25656087A JP25656087A JPH0198235A JP H0198235 A JPH0198235 A JP H0198235A JP 25656087 A JP25656087 A JP 25656087A JP 25656087 A JP25656087 A JP 25656087A JP H0198235 A JPH0198235 A JP H0198235A
Authority
JP
Japan
Prior art keywords
chip
alignment
pattern
electrodes
alignment mark
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25656087A
Other languages
English (en)
Inventor
Yukio Nakamura
幸男 中村
Susumu Umibe
海邊　進
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP25656087A priority Critical patent/JPH0198235A/ja
Publication of JPH0198235A publication Critical patent/JPH0198235A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は情報機器等の電気製品に用いられるＩＣチップ
の実装方法に関するものである。
従来の技術 電気製品の軽薄短小化に伴ないＩＣのパッケージもＤＩ
Ｐ型からフラットパッケージになり、最近ではパッケー
ジのない裸のＩＣチップを実装するようになってきた。
この実装にはＩＣチップのムｌ電極に接続用の五Ｕ等の
玉をメツキ等で付け、これを下側にして実装基板上に熱
圧着していた。
発明が解決しようとする問題点 ＩＣチップを下側にして実装する場合、ＩＣチップが裏
向きになり、ＩＣパターンが見えず、パターンによる位
置合わせが出来ない、したがってＩＣチップのコーナを
使って、位置合わせをするが、コーナ部はＩＯカッティ
ングをＸＣｊパターン面側よりＡ〜係の深さ迄行ない、
その後スクライプするため、その残りの部分にパリが発
生する。
このため、この方法も精度が良くない欠点があった。
この問題を解決するため本発明は簡単にＩＣパターンの
位置合わせが可能な半導体装置の実装方法を提供するも
のである。
問題点を解決するための手段 この目的を達成するため実装基板上または半導体素子上
の少なくともいずれか一方に位置合わせ用のマーキング
を付し、これらのマークを合わせることにより、半導体
素子の位置合わせを行なうものである。
作用 この方法によりＩＣパターンの位置合わせが簡−単に行
なえる。
実施例 以下、本発明の一実施例について図面を用いて説明する
。
第１図は本発明の方法によって実装した半導体装置の断
面図、第２図は本発明の一実施例における半導体装置の
実装方法を示す断面図である。
第１図において、１は基板、２は基板１上に形成された
ランドパターン、３は半田コート、４は位置合わせ用マ
ーク、５は半導体素子７のムｌ電ＩＦＭ６上に形成され
たバンプ、９は樹脂コートである。
次に、第２図を用いて本発明の一実施例における半導体
装置の実装方法について説明する７゜実装するガラスエ
ポキシ等の基板１の表面上にはＧｏ箔のランドパターン
２を形成し、その表面には厚さ１０μ前後の半田コート
３が施こされている。またランドパターン２の中央部に
嬬位置合わせマーク４を作成する。
次にパッケージのない裸のＩＣチップ７をパターン面を
下にして重ねる。
１０チツプ７のパターン面に十字等の位置合わせマーク
４を形成し、これと基板１のマーク４とをＩＣチップ７
の上より赤外線顕微鏡８でＩＣチップ７を透過して合わ
せる。この時ＩＣチップ７の表面に外部電極としてＡｌ
電極６があり、これに電気的接続のためのムＵ等の金属
玉であるバンプ５をメツキ法や転写法等で形成する。次
にＩＣチップ７の上から加熱・加圧しバンプ５と半田コ
ート３を接合させる。最後にＩＣチップ７の保護のため
全面に樹脂コート９をする。
発明の効果 ランドパターンに位置合わせ用マークを施し、位置合わ
せを行うため位置合わせが簡単になる。
【図面の簡単な説明】
第１図は本発明の一実施例における半導体装置の断面図
、第２図は同装置の実装方法を示すｆｆｒ面図である。 １・・・・・・基板、２・・・・・・ランドパターン、
３・・・・・・半田コート、４・・・・・・位置合わせ
用マーク、５・・・・・・バンプ、６・・・・・・Ａｌ
電極、７・・・・・・ＸＯチ・ンプ。 代理人の氏名　弁理士　中　尾敏　男　ほか１名ず−・
−Ｌｘｘ ｆ；−Ａｔ４を罹

Claims (1)

    【特許請求の範囲】
  1. 　実装基板上または半導体素子上の少なくともいずれか
    一方に位置合わせ用のマーキングを付し、それらのマー
    クを合わせることにより半導体素子の位置合わせを行う
    ことを特長とする半導体装置の実装方法。
JP25656087A 1987-10-12 1987-10-12 半導体装置の実装方法 Pending JPH0198235A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25656087A JPH0198235A (ja) 1987-10-12 1987-10-12 半導体装置の実装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25656087A JPH0198235A (ja) 1987-10-12 1987-10-12 半導体装置の実装方法

Publications (1)

Publication Number Publication Date
JPH0198235A true JPH0198235A (ja) 1989-04-17

Family

ID=17294336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25656087A Pending JPH0198235A (ja) 1987-10-12 1987-10-12 半導体装置の実装方法

Country Status (1)

Country Link
JP (1) JPH0198235A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997007538A1 (en) * 1995-08-21 1997-02-27 Mitel Corporation Method of making electrical connections to integrated circuit
JP2007250868A (ja) * 2006-03-16 2007-09-27 Fujitsu Ltd 半導体装置の製造方法および半導体装置
WO2011033797A1 (ja) * 2009-09-18 2011-03-24 ボンドテック株式会社 加圧装置および加圧方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997007538A1 (en) * 1995-08-21 1997-02-27 Mitel Corporation Method of making electrical connections to integrated circuit
JP2007250868A (ja) * 2006-03-16 2007-09-27 Fujitsu Ltd 半導体装置の製造方法および半導体装置
WO2011033797A1 (ja) * 2009-09-18 2011-03-24 ボンドテック株式会社 加圧装置および加圧方法
JP2011066287A (ja) * 2009-09-18 2011-03-31 Bondtech Inc 接合装置および接合方法
EP2479786A1 (en) * 2009-09-18 2012-07-25 Bondtech Co., Ltd. Pressing device and pressing method
EP2479786A4 (en) * 2009-09-18 2013-04-03 Bondtech Co Ltd PRESS DEVICE AND PRESS PROCESS
US9243894B2 (en) 2009-09-18 2016-01-26 Bondtech Co., Ltd. Pressure application apparatus and pressure application method
US9379082B2 (en) 2009-09-18 2016-06-28 Bondtech Co., Ltd. Pressure application apparatus and pressure application method

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