JPH0160864B2 - - Google Patents

Info

Publication number
JPH0160864B2
JPH0160864B2 JP58116014A JP11601483A JPH0160864B2 JP H0160864 B2 JPH0160864 B2 JP H0160864B2 JP 58116014 A JP58116014 A JP 58116014A JP 11601483 A JP11601483 A JP 11601483A JP H0160864 B2 JPH0160864 B2 JP H0160864B2
Authority
JP
Japan
Prior art keywords
memory
dual port
bus
data
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58116014A
Other languages
English (en)
Japanese (ja)
Other versions
JPS608970A (ja
Inventor
Masayuki Tanimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Fuji Facom Corp
Original Assignee
Fuji Electric Co Ltd
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Facom Corp filed Critical Fuji Electric Co Ltd
Priority to JP11601483A priority Critical patent/JPS608970A/ja
Publication of JPS608970A publication Critical patent/JPS608970A/ja
Publication of JPH0160864B2 publication Critical patent/JPH0160864B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)
JP11601483A 1983-06-29 1983-06-29 マルチコントロ−ラシステム Granted JPS608970A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11601483A JPS608970A (ja) 1983-06-29 1983-06-29 マルチコントロ−ラシステム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11601483A JPS608970A (ja) 1983-06-29 1983-06-29 マルチコントロ−ラシステム

Publications (2)

Publication Number Publication Date
JPS608970A JPS608970A (ja) 1985-01-17
JPH0160864B2 true JPH0160864B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-12-26

Family

ID=14676673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11601483A Granted JPS608970A (ja) 1983-06-29 1983-06-29 マルチコントロ−ラシステム

Country Status (1)

Country Link
JP (1) JPS608970A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0324844A (ja) * 1989-06-21 1991-02-01 Fujitsu Ltd パケット転送方式
JP4536618B2 (ja) * 2005-08-02 2010-09-01 富士通セミコンダクター株式会社 リコンフィグ可能な集積回路装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4887741A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1972-02-18 1973-11-17
JPS5178141A (en) * 1974-12-28 1976-07-07 Tokyo Shibaura Electric Co Hyoji kirokusochino batsufuaseigyohoshiki
JPS5857776B2 (ja) * 1979-04-04 1983-12-21 株式会社日立製作所 デ−タ転送装置
JPS5856889B2 (ja) * 1979-12-24 1983-12-17 富士通株式会社 バツファ切替方式

Also Published As

Publication number Publication date
JPS608970A (ja) 1985-01-17

Similar Documents

Publication Publication Date Title
US5408627A (en) Configurable multiport memory interface
JPH01320564A (ja) 並列処理装置
US6308244B1 (en) Information processing apparatus with improved multiple memory access and control
US5845322A (en) Modular scalable multi-processor architecture
JPH0146946B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH0160864B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS59206972A (ja) 共有メモリ
JPH087738B2 (ja) エンディアン変換方式
JP3266610B2 (ja) Ｄｍａ転送方式
JP2640104B2 (ja) データ転送装置
JPH024020B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP2718661B2 (ja) デュアルポートメモリ制御装置
KR970002187B1 (ko) 다수개의 포트를 갖는 레지스터 파일 메모리 구조
JP3743975B2 (ja) 記憶装置システム
JP2636253B2 (ja) 拡張バス方式
JPS63206855A (ja) デ−タ転送装置
JP3038618B2 (ja) テスト用回路を内蔵したメモリ装置
JPH08235054A (ja) 共有メモリ
JPH0426505B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH0552979B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH04258886A (ja) メモリ回路
JPH04263333A (ja) メモリ二重化方式
JPH024024B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH0573470A (ja) デユアル・ポート記憶装置
JPH03116350A (ja) データ転送のバス構造