JPH0152946B2 - - Google Patents

Info

Publication number
JPH0152946B2
JPH0152946B2 JP58220964A JP22096483A JPH0152946B2 JP H0152946 B2 JPH0152946 B2 JP H0152946B2 JP 58220964 A JP58220964 A JP 58220964A JP 22096483 A JP22096483 A JP 22096483A JP H0152946 B2 JPH0152946 B2 JP H0152946B2
Authority
JP
Japan
Prior art keywords
master station
local area
clock pulse
transmission line
lan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58220964A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60113551A (ja
Inventor
Kazuo Nishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58220964A priority Critical patent/JPS60113551A/ja
Publication of JPS60113551A publication Critical patent/JPS60113551A/ja
Publication of JPH0152946B2 publication Critical patent/JPH0152946B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/422—Synchronisation for ring networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Small-Scale Networks (AREA)
JP58220964A 1983-11-24 1983-11-24 ロ−カルエリアネットワ−ク間同期方式 Granted JPS60113551A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58220964A JPS60113551A (ja) 1983-11-24 1983-11-24 ロ−カルエリアネットワ−ク間同期方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58220964A JPS60113551A (ja) 1983-11-24 1983-11-24 ロ−カルエリアネットワ−ク間同期方式

Publications (2)

Publication Number Publication Date
JPS60113551A JPS60113551A (ja) 1985-06-20
JPH0152946B2 true JPH0152946B2 (enExample) 1989-11-10

Family

ID=16759311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58220964A Granted JPS60113551A (ja) 1983-11-24 1983-11-24 ロ−カルエリアネットワ−ク間同期方式

Country Status (1)

Country Link
JP (1) JPS60113551A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63102524A (ja) * 1986-10-20 1988-05-07 Fujitsu Ltd マスタクロツク源の二重化接続方法

Also Published As

Publication number Publication date
JPS60113551A (ja) 1985-06-20

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