JPH0151104B2 - - Google Patents

Info

Publication number
JPH0151104B2
JPH0151104B2 JP58184014A JP18401483A JPH0151104B2 JP H0151104 B2 JPH0151104 B2 JP H0151104B2 JP 58184014 A JP58184014 A JP 58184014A JP 18401483 A JP18401483 A JP 18401483A JP H0151104 B2 JPH0151104 B2 JP H0151104B2
Authority
JP
Japan
Prior art keywords
clock
output
input
frequency
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58184014A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6075148A (ja
Inventor
Takashi Nara
Hiroaki Takechi
Masami Murayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58184014A priority Critical patent/JPS6075148A/ja
Publication of JPS6075148A publication Critical patent/JPS6075148A/ja
Publication of JPH0151104B2 publication Critical patent/JPH0151104B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP58184014A 1983-09-30 1983-09-30 クロツク整形回路 Granted JPS6075148A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58184014A JPS6075148A (ja) 1983-09-30 1983-09-30 クロツク整形回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58184014A JPS6075148A (ja) 1983-09-30 1983-09-30 クロツク整形回路

Publications (2)

Publication Number Publication Date
JPS6075148A JPS6075148A (ja) 1985-04-27
JPH0151104B2 true JPH0151104B2 (enrdf_load_stackoverflow) 1989-11-01

Family

ID=16145819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58184014A Granted JPS6075148A (ja) 1983-09-30 1983-09-30 クロツク整形回路

Country Status (1)

Country Link
JP (1) JPS6075148A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE63793T1 (de) * 1985-05-15 1991-06-15 Siemens Ag Schaltungsanordnung zur rueckgewinnung des taktes eines isochronen binaersignales.

Also Published As

Publication number Publication date
JPS6075148A (ja) 1985-04-27

Similar Documents

Publication Publication Date Title
US6359945B1 (en) Phase locked loop and method that provide fail-over redundant clocking
US5373254A (en) Method and apparatus for controlling phase of a system clock signal for switching the system clock signal
JP3066690B2 (ja) 位相同期発振回路
JP3084151B2 (ja) 情報処理システム
JPH04234225A (ja) デジタル位相ロックトループ
JP2002217715A (ja) ヒットレス基準切替えを用いた多重入力位相同期ループ
JPH07235873A (ja) クロック発生用回路装置
US6333678B1 (en) Method and apparatus for agile phase noise filtering using phase locked loops
US6166606A (en) Phase and frequency locked clock generator
JPH0151104B2 (enrdf_load_stackoverflow)
JPS58139227A (ja) クロツク供給回路の切替方式
JP3712141B2 (ja) 位相同期ループ装置
JPH08331085A (ja) ディジタル位相同期回路及びこれを用いたデータ受信回路
JPH05199498A (ja) クロツク発生回路
JP2000244311A (ja) クロック切替調整方法及び回路
JP2795008B2 (ja) 位相同期発振回路の耐入力クロック断回路方式
JPS6281177A (ja) 同期制御回路
JPS6333739B2 (enrdf_load_stackoverflow)
JPS61144124A (ja) Ｐｌｌ同期回路
JPH04291819A (ja) 位相同期ループ回路及び基準信号選択回路
JPH04183119A (ja) クロック再生回路
JPH03272234A (ja) 従属同期方式
JPH03185925A (ja) クロック周波数変換装置
JPH05110552A (ja) データ伝送装置
JPH0134414B2 (enrdf_load_stackoverflow)