JPH0131225B2 - - Google Patents

Info

Publication number
JPH0131225B2
JPH0131225B2 JP831584A JP831584A JPH0131225B2 JP H0131225 B2 JPH0131225 B2 JP H0131225B2 JP 831584 A JP831584 A JP 831584A JP 831584 A JP831584 A JP 831584A JP H0131225 B2 JPH0131225 B2 JP H0131225B2
Authority
JP
Japan
Prior art keywords
memory
data
control unit
bus
adapter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP831584A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60160459A (ja
Inventor
Kentaro Myoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP831584A priority Critical patent/JPS60160459A/ja
Publication of JPS60160459A publication Critical patent/JPS60160459A/ja
Publication of JPH0131225B2 publication Critical patent/JPH0131225B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP831584A 1984-01-20 1984-01-20 直接メモリ・アクセス制御方式 Granted JPS60160459A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP831584A JPS60160459A (ja) 1984-01-20 1984-01-20 直接メモリ・アクセス制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP831584A JPS60160459A (ja) 1984-01-20 1984-01-20 直接メモリ・アクセス制御方式

Publications (2)

Publication Number Publication Date
JPS60160459A JPS60160459A (ja) 1985-08-22
JPH0131225B2 true JPH0131225B2 (enrdf_load_stackoverflow) 1989-06-23

Family

ID=11689718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP831584A Granted JPS60160459A (ja) 1984-01-20 1984-01-20 直接メモリ・アクセス制御方式

Country Status (1)

Country Link
JP (1) JPS60160459A (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63120242A (ja) * 1986-11-07 1988-05-24 Nec Corp 粘性測定装置
JPH0651932U (ja) * 1992-12-18 1994-07-15 ミツミ電機株式会社 インタフェース回路
US7213084B2 (en) 2003-10-10 2007-05-01 International Business Machines Corporation System and method for allocating memory allocation bandwidth by assigning fixed priority of access to DMA machines and programmable priority to processing unit

Also Published As

Publication number Publication date
JPS60160459A (ja) 1985-08-22

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