JPH01292438A - Interruption processor - Google Patents

Abstract

PURPOSE:To surely attain the execution of interruption within a fixed hour without allowing an interruption signal with the highest interruption level to always monopolize interruption by constituting the title processor so that the interruption level indicating interruption is changed together with time. CONSTITUTION:Until time arrives at t1 after starting the operation of a device, a counter 22 outputs a signal indicating degree of urgency C (C<B<A). When an interruption request signal IRQ is applied during the output of the signal, an interruption level selector 31 outputs an interruption request IRQ5 with level 5. The interruption signal is applied to a microprocessor 1. However, the processor 1 does not receive the interruption request until a fixed time t1 passes. After the passage of the time t1, the counter 22 outputs degree of urgency B. When the processor 1 does not still receive the interruption, the counter 22 outputs a signal indicating degree of urgency A after the passage of a prescribed time and outputs an interruption request signal IRQ7 with the highest interruption level to execute interruption processing.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an interrupt processing device applied to a microprocessor device having an interrupt function. The present invention relates to an interrupt processing device that can reliably process interrupts within a certain amount of time.

(Prior art) Microprocessor devices that are capable of processing work in real time need to
It is equipped with an interrupt means so that changes in external events can be detected asynchronously. This interrupt means has several interrupt lines, among which priorities (interrupt levels) are fixedly assigned on a one-to-one basis.

(Problem to be solved by the invention!!!) By the way, in the conventional device configured in this way, for example, when receiving a communication, the time interval between interrupt occurrences is relatively long, and it is not possible to reliably interrupt within a certain period of time. When processing work that requires receiving data, it is difficult to decide which interrupt level to assign to it, because in order to reliably receive data,
You can raise the interrupt level, but doing so will affect the efficiency of other interrupt processing, and lowering the interrupt level will cause the problem that data cannot be received or received within a certain amount of time. This is because it occurs.

The present invention has been made in view of these points, and its purpose is to realize an interrupt processing device that can efficiently process interrupts by changing the interrupt level according to the degree of temporal urgency. It is in.

(Means for solving the problem) FIG. 1 is a basic block diagram of the present invention. In FIG. 0, 1 is a microprocessor that receives external interrupts and processes work in real time; Urgency level setting means 3 for setting a dependent level of urgency inputs the level of urgency from this level of urgency setting means 2 and also outputs an interrupt signal I.
This is an interrupt level selection means that receives an RQ and determines a predetermined interrupt level according to the degree of urgency.

(Function) The urgency level setting means 2 is set in advance so that, for example, the degree of urgency increases with the passage of time, and the interrupt level selection means 3, when receiving an interrupt, selects the level of urgency according to the level of urgency from the urgency setting means. An interrupt is issued to the microprocessor 1 at the interrupt level set.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 0, the same components as in FIG. 1 are designated by the same reference numerals.
0 or MC68020 is used.

The urgency setting means 2 includes a time setting register 21 in which the interrupt acceptance cycle required by Ilo that makes the interrupt and the degree of urgency based on time are set, and when the time according to the contents of the time setting register 21 arrives, the interrupt acceptance period and the urgency level according to time are set. It is composed of a counter 22 that outputs signals A, B, and C indicating a certain degree of urgency.

The interrupt level selection means 3 includes an interrupt level selector 31 that receives an external interrupt request signal IRQ and controls which priority level the signal is outputted to, a vector register 32 in which the user has stored data related to the interrupt contents, and a rear. It includes a controller 33 that receives the interrupt confirmation signal described in 2 and notifies the microprocessor 1 of the contents of the vector register 32 via the data bus BS.

These urgency setting means 2 and interrupt level selection means 3 are both connected to the microprocessor 1 via a data bus BS.

4 is an interrupt controller, which is connected to an external Ilo (not shown).
(7 levels of interrupts are prepared according to their priorities), and an interrupt level encoder 41 encodes this interrupt request signal according to the priority.
and an IACK cycle controller 42 to which an interrupt control line from the microprocessor 1 is connected, outputs an interrupt acknowledgment signal to the controller 33, and controls the interrupt cycle.

The operation of the device configured in this way will be explained next.

FIG. 3 is a timing chart showing an example of the operation. Here, the interrupt acceptance cycle is from tO to t3 hours, and the degree of urgency based on time is 5 levels between tO and t1, and t
It is assumed that 6 levels are set between 1 and t2, and 7 levels are set between t2 and t3.

Initially, the device starts operating and until it reaches tl,
As shown in (a), the counter 22 outputs a signal indicating the degree of urgency C (the degree of urgency is assumed to be C<B<A). During this time, when the interrupt request signal IRQ is applied as shown in (d), the interrupt level selector 31 outputs a 5-level interrupt request signal IRQ5 as shown in (e). This interrupt request signal is encoded by the interrupt level encoder 41 and applied to the microprocessor 1 as an interrupt signal IPL2.

However, during this time, the microprocessor 1 does not accept this interrupt request, and time t1 elapses.

Then, the counter 22 outputs a signal indicating the degree of urgency B (
1 interrupt level selector 31 that outputs as shown in b)
receives this signal indicating the urgency level B, then (f)
As shown in FIG. 3, a 6-level interrupt request signal IRQ6 having a higher priority than before is output.

However, the microprocessor 1 still does not accept this interrupt request, and time t2 elapses.

Subsequently, the counter 22 outputs a signal indicating the degree of urgency A (c).
1 interrupt level selector 31 outputs as shown in
When receiving the signal indicating the degree of urgency A, the interrupt request signal IRQ7 of the 7th level with the highest priority is output as shown in (g). Interrupt level encoder 4 that received this
1 applies a non-maskable interrupt signal IPLO to the microprocessor 1. Microprocessor 1 is
This ensures that interrupts are accepted, the interrupt cycle is controlled, and the controller 42 receives the acknowledgment signal IAC.
K is output to the controller 33 as shown in (h).

In response to this, the controller 33 controls the vector register 32
The data indicating the contents of the interrupt stored in the microprocessor 1 is sent to the microprocessor 1 via the data bus BS, and the microprocessor 1 processes the interrupt. The counter 22 is then cleared by a clear signal CLR output from the controller 33.

(Effects of the Invention) As explained above in detail, the present invention is configured such that the interrupt level changes over time, and no matter what kind of work the microprocessor is processing, the interrupt level remains constant for a certain period of time. Interrupts are reliably accepted within this period, and since the interrupt does not always occupy a high interrupt level, it does not affect other highly urgent interrupt processing.

Therefore, according to the present invention, it is possible to provide an interrupt processing device that can efficiently process interrupts.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration block diagram of the present invention, FIG. 2 is a configuration block diagram showing an embodiment of the present invention, and FIG. 3 is a timing chart showing an example of the operation. 1...Microprocessor 2...Urgency level setting means 21...Register 22...Counter 3...Interrupt level selection means 4...Interrupt controller FIG.

Claims (1)

[Claims] An interrupt processing device that processes work in real time in response to an external interrupt, comprising: an urgency setting means for setting a time-dependent degree of urgency; and an input of the urgency from the urgency setting means. An interrupt processing device characterized in that it is further provided with an interrupt level selecting means for receiving an interrupt signal and determining a predetermined interrupt level according to the degree of urgency.