JPH03273437A - Interruption processor - Google Patents

Abstract

PURPOSE:To realize efficient interruption control by selecting the degree of priority corresponding to the interruption request of the highest degree of priority from among the degree of priority of the requests by the input of the interruption request, and outputting it to a level selecting device. CONSTITUTION:The level selecting device 11 outputs the request level '5' of 1RQ5 by the instruction of a request selecting device 10. When it is informed that the request of 1RQ5 was accepted through interruption permission input 3, the bits corresponding to 1RQ5 of a request register 2 and a queuing request register 7 are reset, and in a counter 9, the request level of 1RQ5 is returned from '1' to '5'. When all the interruption request registered in the request register 2 are accepted, all the bits of the request register 2 and the queuing request register 7 are turned into '0', and the level held in the counter 9 comes to a value equal to the value of the request level 8 of the degree of priority of the first interruption request. Thus, the efficient interruption control to keep the regularity of a whole system can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an interrupt processing device using a dynamic priority determination method that adds a waiting time for interrupt requests in a data processing device in which a plurality of interrupt requests exist. .

2. Description of the Related Art As an interrupt management method used in general data processing devices, there is a method of changing the request level as time passes from when an interrupt request is generated until the interrupt is permitted. in this case,
Interrupts with variable interrupt request levels: If there is an interrupt that is currently being processed and the interrupt is enabled, the new interrupt is enabled when the request level of the new interrupt becomes higher than this interrupt. It is a processing device.

In this conventional device, the request level increases as the waiting time elapses, and an interrupt with a low request level at the beginning of the interrupt request interrupts an interrupt with a high request level.
Interrupts with a lower initial priority finish processing first, and interrupts with a higher priority are placed in a waiting state, which may affect the integrity of the system.

Furthermore, if the central processing unit masks interrupts below a certain level, the request level changes dynamically, making it impossible to implement level-based mask management.

In this way, in conventional interrupt processing devices, there is no upper limit to the counter that changes the request level over time, so an interrupt request that has been in a waiting state for a long time becomes the highest level request, and the counter changes the request level over time. In an interrupt processing method, if the highest level request is a non-maskable interrupt, an interrupt that has elapsed for a long time as described above will be processed as a non-maskable interrupt.

In addition, in a conventional system that uses multiple interrupt processing devices connected, the interrupt request level changes at the time the interrupt permission is granted while the interrupt permission is being propagated. This has problems such as the possibility that the cycle cannot be executed.

Problems to be Solved by the Invention As described above, in a data processing device using a conventional interrupt processing device, when multiple interrupt requests are made, priority is determined based on the initial need for high-speed processing. , with the addition of priority changes based on latency, when interrupts with initially low priority levels slow down to the highest priority level in some cases, and interrupts that require high-speed processing occur later. This poses the problem of causing inconveniences such as being postponed.

The present invention takes the above-mentioned problems into consideration, and achieves a balance between the need for high-speed processing and the priority given to waiting time in a data processing device.
The present invention aims to provide an interrupt processing device that performs efficient interrupt control without impairing the regularity of the system.

Means for Solving the Problems In order to achieve the above object of the present invention, in a data processing device in which a plurality of interrupt requests exist, a plurality of interrupt request inputs are detected and registered, and an interrupt is already enabled. There is a request register that deletes the interrupt request for which an interrupt enable signal has been input, and a count pulse is generated when an interrupt request input is registered in this request register, and the count pulse is counted using this count pulse and a constant value is generated. A timer that outputs a signal when the interrupt request is reached, inputs the contents of the request register at the timing of this timer's output, inputs the waiting request register to register, the request priority by the initial interrupt request input, and the output of the waiting request register. , the priority of the interrupt request registered in the waiting request register is changed one level at a time according to the timer output timing until it reaches a certain level, and the changed priority is maintained, and the priority of the interrupt request registered in the waiting request register is changed one level at a time until it reaches a certain level. As a result, for interrupt requests for which an interrupt permission signal has been input, input a counter that returns the changed priority to the priority of an interrupt request whose priority does not increase due to the initial waiting time, and input the contents of this counter. A request selection device determines the interrupt request with the highest priority, and a request priority based on the output of this request selection device and the initial interrupt request input is input, and the priority corresponding to the interrupt request with the highest priority is selected. It is equipped with a level selection device for output.

Further, the level selection device selects and outputs the priority to be output as the request priority due to the initial input of the interrupt request, that is, the priority that is not increased due to the waiting time by the counter.

Furthermore, an upper limit is set for increasing the priority according to the waiting time by the counter, and until the upper limit is reached, the priority increases by one level at the timing of the timer output, and when the upper limit is reached, priority is given no matter how much the waiting time increases. There is no increase in degree.

Operation In the interrupt processing device of the present invention having the above configuration, when an interrupt request is made and the interrupt request is not permitted, first the input system and the priority of the interrupt request for each system are set in the request register. Therefore, input to a certain input system corresponding to that interrupt request, and then input to that system.

It is registered as a standard interrupt request. If there is something that is already being processed due to interrupt permission, etc., the contents of the request register are transferred to the waiting request register at the output timing from the timer.

The timer inputs a count pulse that is output as long as there is a waiting interrupt request in the request register, and outputs a signal every time the count reaches a certain value.

The request registered in the waiting request register is output from the timer and is transferred to the counter at the timing of a signal inputted with a certain delay from the signal inputted to the waiting request register.

In the counter, the priority of the initial interrupt request of this registered request is increased by one level, for example, at the timing of the signal from the timer that is output at a certain interval, and the priority is set according to the waiting time of the request. We will continue to improve our level.

There is an upper limit to this priority increase; beyond a certain value, the priority will not increase no matter how much the waiting time increases.

When the priority increases due to this waiting time and becomes higher than the priority of other interrupt requests, the request selection device recognizes that the interrupt request has the highest priority.

The level selection device inputs the highest priority interrupt request and inputs the priority of the initial interrupt request, that is, the priority before the priority increase due to waiting time is added, so it selects the priority from among them. , selects and outputs the one corresponding to the interrupt request system.

An interrupt permission signal is issued by the output of this level selection device, and this signal is inputted to the request register, waiting request register, and counter.

As a result of this interrupt permission input, the request register and the waiting request register reset the input system to the initial state since the interrupt request of that input system has been processed. The counter also returns to its initial state by returning the priority of that system, which has been increased due to the waiting time, to its initial, preset value.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, in this embodiment, a plurality of interrupt request input signals 1 having seven input systems are input to the request register 2, which detects the interrupt input and sets the bit corresponding to the requested input. and hold. Further, the interrupt permission manual 3 resets the bit corresponding to the permitted request in the request register 2.

By inputting the initial value to the timer 5 and by the timer manual power 4 that controls the count pulse, the timer 5 counts down according to the count pulse manual power 4, and the count value is all 0.
When this happens, timer output 6A is enabled.

The waiting request register 7 inputs and holds the value of the request register 2 in synchronization with the timer output 6A, when the input interrupt request is
Indicates that the state has been waiting for interrupt permission for a certain period of time or more.

In this embodiment, request level 8 corresponding to the interrupt request has seven levels, with level 0 having the highest priority.

The request level of the input 8 is input, and in synchronization with the timer output 6B, the request level of the request waiting for an interrupt is subtracted one level at a time in the waiting request register 7, and the counter 9 that is held sets the subtraction level. This ensures that the level does not fall below the set level.

Furthermore, a request selection unit 1O and a request selection unit 10 determine the request with the highest priority among the levels held in the counter 9.
The level selection device 11 selects the request level 8 corresponding to the bit of the request determined by and outputs the interrupt level 12. When there is no interrupt request, the level selection device 11
produces output indicating that there is no request.

Regarding the interrupt processing device configured as above, the related operations of its constituent elements will be explained below.

The timer 5 is set to a certain value as the initial value, and the count pulse manual 4 is stopped, so the timer 5 is not operating.The interrupt request input signal 1 is 7 bits of IRQO-IRQ6, For input, required levels as shown in FIG. 2 are arranged in bits and set in advance. Level 0 is the highest priority and level 6 is the lowest priority.

Since the subtraction level of the counter 9 is set to 1, the level 1 or higher among the required levels 8 will never become level 0.

Assuming that interrupt inputs IRQ4 and IRQ5 are input to the interrupt processing device initialized as above,
Request register 2 has IRQ4 and I
The bit corresponding to RQ5 is set.

When a value is set in the request register 2, a count pulse 4 of the timer 5 is generated (the count pulse output circuit is not involved), and the timer 5 starts counting down.

Since the outputs 6A and 6B of the timer do not become valid until the timer 5 becomes all O's, all bits of the wait request register 7 are in the state of O's.

The counter 9 receives the request level 8 and the value of the waiting request register 7, and holds the input request level 8 until the timer output 6B becomes valid.

The request selection device 10 inputs the value held by the counter 9 and the value of the request register 2, compares the request levels of IRQ4 and IRQ5, and notifies the level selection device 11 that IRQ4 is the highest priority request.

The level selection device 11 outputs "4" which is the requested level corresponding to IRQ4.

When notified by the interrupt enabler 3 that the interrupt request for IRQ4 has been accepted (the interrupt enable output circuit is not shown), the request register 2 resets the bit corresponding to IRQ4.

The counter 9 returns the counted down request level to the original request level by the interrupt permission manual 3, but the held level does not change because the timer output 6B does not count.

Since the request for IRQ5 remains in the request register 2, the timer 5 continues counting down, and when the count value reaches all O's, a timer output/curse 6A is generated.

In synchronization with the timer output pulse 6A, the bit corresponding to IRQ5 of the wait request register 7 is set.

Since the timer output pulse 6B is delayed with respect to the timer output pulse 6A, when the timer output pulse 6B is input to the counter 9, the already set value of the wait request register 7 is input, so that the value of the IRQ5 is The request level is “
5" → "4" and increase the priority of IRQ5.

When the count value reaches all 0, the timer 5 inputs an initial value and starts counting down again.

Timer 5. The waiting request register 7 and the counter 9 continue the above operations until there are no more requests in the request register 2.

The timer output pulse 6B causes the counter 9 to output IR.
When the requested level of Q5 corresponds to IRQ5 in the bit arrangement in the counter 9 shown in Fig. 4 is subtracted, and the requested level of IRQ5 held in the counter 9 becomes 1'', no further subtraction is performed. .

When a request for IRQ5 is in a waiting state and the request level held in counter 9 is "1", IRQo.

When an interrupt request other than IRQ1 occurs and is registered in the request register 2, the request selection device 10 recognizes that the request level of IRQ5 is "1" and has the highest priority.

The level selection device 11 outputs the request level “5” of IRQ5 according to the instruction from the request selection device 10.

Interrupt permission human power 3 indicates that the request for IRQ5 has been accepted.
When notified by , the bit corresponding to IRQ5 in the request register 2 and waiting request register 7 is reset, and the counter 9 returns the request level of IRQ5 from "1" to "5".

When all the interrupt requests registered in the request register 2 are accepted, all bits in the request register 2 and waiting request register 7 become O, and the level held in the counter 9 is the priority of the original interrupt request. The value is the same as the value of request level 8, which is .

Note that when an IRQO or IRQI interrupt request occurs, the request level of the counter 9 does not exceed "1", so naturally the IRQO or IRQI interrupt request is given priority.

In this way, it is possible to promptly process the interrupt request that is the highest priority emergency processing request, and to perform efficient interrupt processing that also takes into account the waiting time factor.

Effects of the Invention As is clear from the above explanation, according to the present invention, an element for increasing the priority level of an interrupt request by waiting time and an element for adding an upper limit value to the increase are provided, and the priority level of the interrupt request is increased. Interrupt requests for emergency processing requests can be processed promptly, and the interrupt request can be processed with waiting time taken into account. Interrupt management can be performed while maintaining the original priority of the interrupt request, so the overall system Efficient interrupt control that maintains regularity can be realized.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of an interrupt processing device according to an embodiment of the present invention, Fig. 2 is a bit arrangement diagram showing the request level set in the embodiment, and Fig. 3 is a bit arrangement diagram showing the request level set in the embodiment. Bit arrangement diagram in the registered request register, 4th
The figure is a bit arrangement diagram showing changes in the level held in the counter of the same embodiment. l...Interrupt request input, 2...Request register, 3...Interrupt permission input, 4...Count pulse input, 5... ...Timer, 6A, 6B
...Timer output pulse, 7...Waiting request register, 8...Request level, 9...
Counter, 10...Request selection device, 11...
. . . Level selection device, 12 . . . Interrupt level.

Claims (2)

[Claims] (1) A request register that detects and registers a plurality of interrupt request inputs and deletes an interrupt request that has been permitted by an input indicating interrupt permission, and when the interrupt request input is registered in the request register. a timer that inputs a generated count pulse and outputs a signal when it counts and reaches a certain value; a wait request register that inputs and registers the contents of the request register at the output timing of the timer; and the interrupt request. inputting the request priority and the contents of the waiting request register, changing the priority level of the interrupt request registered in the waiting request register one level at a time at the output timing of the timer until it reaches a certain level; a counter that holds the changed priority and returns the changed priority to the priority of the interrupt request registered in the waiting request register upon input indicating permission for the interrupt; and inputting the contents of the counter; a request selection device that determines an interrupt request with the highest priority; and a request selection device that inputs the request priority based on the interrupt request input and the output of the request selection device, and determines the priority corresponding to the interrupt request with the highest priority. The level selection device includes a level selection device that selects and outputs a priority corresponding to the highest priority interrupt request from among the request priorities obtained by inputting the interrupt request. An interrupt processing device having: (2) The interrupt processing device according to claim 1, wherein the priority level is changed by a counter such that the priority level increases by one level at the output timing of a timer, and the increase has an upper limit value.