JPS629441A - Timer interruption control system - Google Patents

Abstract

PURPOSE:To attain a timer interruption control at high speed by providing bit '0' to both firmware and hardware as the interruption conditions and copying the bit '0' of the firmware timer to the hardware timer through a timer device. CONSTITUTION:A timer device produces an interruption factor to the processor of a computer system. In such a timer device the bit '0' is set to both firmware 2 and hardware 2 as the interruption conditions to the processor. Here the bits '0' and '200' of the firmware timer 2 which are set with the replacement timing can be copied to bits '0' and '10' of the hardware timer 1. Thus the interruption processing is performed at the high speed by a CPU timer.

Description

[Detailed Description of the Invention] [Summary] In a timer device that generates an interrupt factor for a processor of a computer system, a lower bit part that is always counted down or counted up is configured with hardware, and it is possible that the lower bit part does not operate for a certain period of time. In a timer device in which the guaranteed part is configured by firmware, etc., the most significant bit 0°, which is the interrupt condition for the timer to the processor, is provided in both the firmware and the hardware, and is configured by the firmware. The value of bit 0'' of the interrupt condition set at the update timing for the timer is copied to bit 0'' of the timer configured by hardware.

[Industrial application field]

The present invention relates to a control method for bit 0, which is an immediate interrupt condition for a processor in a computer system.

With the recent spread of online computer systems,
The number of jobs that need to be processed in real time is increasing, and there is a demand for faster responses to interrupt processing caused by commands input from multiple user terminals.

However, the computer system is equipped with a so-called "R CPU timer", which always operates in real time, and measures the execution time for jobs executed by each user, or processes multiple batches from each user. It is used as a timer interrupt to equalize services to multiple users by returning the job to the monitor after it has been executed for a certain period of time.

When configuring such a ``R CPU timer,'' from the viewpoint of economy, it is usually configured in such a way that the counting time is shared between hardware and software such as firmware.

In this case, for example, there is a method of counting down from a certain value and setting it as a timer interrupt when the most significant bit becomes 1", but this interrupt If it takes time to process the firmware to determine whether the most significant bit is °0/1, which is the condition, this process is a real-time process and other interrupts are prohibited, so the impact on other interrupt processes will be large. As a result, there is a problem in that the response to command input from the user terminal becomes slow, and a control system that speeds up the execution time of firmware processing by the RCPU timer as much as possible has been awaited.

[Conventional technology]

Figure 3 is a block diagram showing an example of the configuration of a conventional rcpu timer, where (a) shows the part made up of hardware, and (b) shows the part made up of firmware, for example. ing.

Usually, the hardware timer 1 in (a) is, for example, 1 μ
A counter that counts up or down the real time signal of s, and is configured to generate an interrupt to the firmware when a carry signal or borrow signal is output from its most significant bit 10'. .

In the interrupt processing from the hardware timer 1, the high-order bit of the above-mentioned "r cpu timer" provided in the register A20 of the arithmetic circuit shown in (b), for example, in a specific area of the local storage (LS) 23. Read the contents (T) of the local storage (LS)
23 - For example, after reading out all degrees 1 to register B 21 - Arithmetic unit (^LU)
22, and the addition result is stored in the timer area of the local storage (LS) 23 through register A, thereby completing the single count operation.

In this way, when the most significant bit (M) of the firmware timer is set to 1, an interrupt to the processor of the rcpu timer occurs.

In such a r cpu timer, the number of bits of the hardware timer (counter) 1 may be reduced (this will reduce the amount of hardware, but the burden on the firmware will become heavier, resulting in a decrease in the performance of the computer system). Become.

(2) Conversely, if the number of bits of the hardware timer (counter) l is increased, the amount of hardware will increase, but the performance will be less degraded.

Therefore, in general, if the hardware timer is configured with about 20 bits and is configured to count 1 μs real-time signals as described above, the interrupt period for the firmware will be about 1 second, and the execution of 1 microinstruction will be In a computer system where the time is about 100 ns, the interrupt frequency is about IMIPS (once per million instructions), and the influence of the r cpu timer on firmware can be ignored.

[Problem that the invention seeks to solve]

However, in the conventional method, as mentioned above, once the interrupt processing of the r cpu timer is started,
In other words, the counting process for the firmware timer (T) provided in a specific area of the local storage (LS) 23, and the counting process for the firmware timer (T) provided in a specific area of the local storage (LS) 23, as well as the counting process for the firmware timer (T) provided in a specific area of the local storage (LS) 23. Until a series of micro interrupt processing such as judgment processing is completed, other interrupts,
For example, there is a problem in that interrupt processing accompanying a command input from a user terminal is made to wait, slowing down the response to the command input from the user terminal.

In view of the above conventional drawbacks, the present invention speeds up micro-interrupts from the hardware timer part of the CPU timer, firmware processing associated with the interrupts, speeds up the overall interrupt processing for the processor, and enables command input from the user terminal. The purpose is to provide a method for speeding up responses to

[Means for solving problems]

FIG. 1 is a principle block diagram of the "R CPU timer" of the present invention, where 1 is a hardware timer and 2 is a firmware timer.

Bit O, which is the condition for timer interrupt to the processor, is set to 200 for firmware and 1 for hardware.
0 and firmware timer 2 carries from hardware timer 1.

Or when a micro interrupt occurs due to a borrow signal, after counting up or down the firmware timer 2, the value of bit O'200 of the firmware is set to bit 0 of the hardware.
10.

[Effect]

That is, according to the present invention, in a timer device that generates an interrupt factor for a processor of a computer system, the lower bit part that is always counted down or count-amplified is configured with hardware, and is guaranteed not to operate for a certain period of time. In a timer device whose part is configured with firmware or the like, the most significant bit O゛ of the timer, which is the interrupt condition for the processor, is
It is provided in both firmware and hardware, and the value of bit 0 of the above interrupt condition, which is set at the update timing for the timer configured in firmware, is copied to bit 0 for the timer configured in hardware. This eliminates the need for microsteps to check °0/1' for °bit 0° of the firmware timer, and even in computer systems that do not have a bit check mechanism, the rcpu timer
This has the effect of speeding up interrupt processing for the processor.

〔Example〕 Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. The same reference numerals as in FIGS. The mechanism for copying to bit O''10 is the mechanism necessary to implement the present invention.

Even if the present invention is implemented, the operations of the hardware timer, that is, the counter 1, and the counting operation of the firmware timer 2 are the same as in the conventional system, so they will be omitted. The timer interrupt control method of the present invention will be explained with a focus on its operation.

First, when the count operation of firmware timer 2 is performed by a micro interrupt caused by a carry signal from counter l or a borrow signal, the calculation result is stored in register A.
After setting it to 20, for example, local storage (
LS) At the timing to store it in the firmware timer area (T) of 23, the value of bit O'200 (indicated by diagonal lines), which is the most significant bit, is stored in bit O'10 of hardware timer (counter) 1. control to copy to.

As a result, the interrupt condition for "r cpu timer" is
"Bit O" can be transferred to a hardware interrupt source (not shown), and then a high-speed interrupt to the processor can be performed according to the priority mechanism in the interrupt processing circuit.

Furthermore, as soon as the counting process in firmware timer 1 is completed, the "bit O" 200 can be copied to "bit 0'10" of the hardware timer, which was previously done.
Without checking the value of bit 0”200 above,
Processor interrupts can be executed by the "r cpu timer".

As described above, in the present invention, in a timer device in which the "rcpu timer" provided in a computer system is divided into a hardware timer and a firmware timer, "bit 0", which is an interrupt condition for the processor, is configured. is provided in both firmware and hardware, and the firmware timer's bit Q' obtained at the update timing of the firmware timer is copied to the hardware timer's bit 0°.

〔Effect of the invention〕

As described above in detail, the timer interrupt control method of the present invention configures the lower bit part, which is always counted down or counted up, in hardware in a timer device that causes an interrupt factor to a processor of a computer system. In a timer device in which a part that is guaranteed not to operate for a certain period of time is configured with firmware, etc., the most significant bit Q' of the timer, which is the interrupt condition for the processor, is set by both the firmware and the hardware. , and is set at the update timing for the timer configured in the firmware.
The value of bit Q of the above interrupt condition is copied to bit O of the timer configured in hardware, so the firmware timer's
This eliminates the need for a microstep for the 0/19 check on bit O', and has the effect of speeding up interrupt processing for the processor by the rcpu timer even in a computer system that does not have a bit check mechanism.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the "rcpu timer" of the present invention. FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 3 is a block diagram showing a configuration example of a conventional rcpu timer. It is. In the drawing, 1 is a hardware timer (counter). 2 is the firmware timer. 20 is register A, 21 is register B. 22 is an arithmetic unit (ALU). 23 is local storage (LS). T is the contents of the firmware timer. 200 is the firmware timer's bit O' (M)
. 10 is bit Ql of the hardware timer. are shown respectively. 7゛-1'7''''7 force 9□□ length 9□□9jPIJ5
'4? p@J! 7D, y7a child 1 prisoner

Claims (1)

[Claims] In a timer device that generates an interrupt factor for a processor of a computer system, the lower bit part that always operates is configured with hardware (1), and the upper bit part is guaranteed not to operate for a certain period of time. This is a timer device whose part is configured with firmware or software, and a bit (10) for hardware is provided in addition to the bit (200) for the firmware or software that is the interrupt condition from the timer device.
Or, when updating the timer by software, the above firmware or software interrupt condition bit (200
) is set to the above hardware interrupt condition bit (1
0).