JPH05210515A - Instruction interruption priority processor - Google Patents

Abstract

PURPOSE:To solve a problem that instructions of a certain system are not executed because of low priority in a device which accepts instructions from plural systems and processes them preferentially. CONSTITUTION:A counter A5 counts the waiting time of an issued instruction of a device A1 which is held in an interruption buffer A3. A counter B6 counts the waiting time of the issued instruction of the device B2 which is held in an instruction buffer B4. A priority processing circuit 7 inputs a waiting instruction A signal 105, a waiting instruction B signal 107, an interruption A signal 109, and an interruption B signal 110, processes the instructions preferentially while giving higher priority to whether there is an interruption or not than to the kinds of the instructions, and sends a resetting signal to the instruction buffer of the system corresponding to the processed instruction. A control circuit 8 inputs an instruction and system number signal 111, and sets an in-instruction- execution busy signal 114 to '1' to inhibit a priority processing circuit 7 from operating.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction interrupt priority processing apparatus in an apparatus that receives instructions from a plurality of systems.

[0002]

2. Description of the Related Art A conventional priority processing apparatus for instructions will be described with reference to FIG. As a conventional example, the number of systems that issue instructions is limited to two.

Referring to FIG. 2, the conventional device is device A
The instruction A signal 101 from 1 is held, the waiting instruction A signal 105 is output, and the instruction after execution is reset A signal 106
An instruction buffer A3 which is reset by means of the instruction buffer A4, an instruction buffer B4 which holds the instruction B signal 102 from the device B2 and outputs a waiting instruction B signal 107, and which resets the executed instruction by means of the reset B signal 108; When the busy signal 114 indicating “0” is stopped and the busy signal 114 indicates “0” which is not in operation, the instruction for selecting which of the wait instruction A signal 105 and the wait instruction B signal 107 should be executed first Priority output based on type, etc. and output command / system number signal 111, and output reset A signal 106 or reset B signal 108 to reset the contents of command buffer 3 or 4 of the system that issued the selected command. The processing circuit 7 and the command / system number signal 111 are input, the busy signal 114 is output as "1" only while the command is being executed, and the system that issued the accepted command is instructed. And a control circuit 8 for outputting a command acceptance notification A signal 112 or instruction acceptance notification B signal 113 for notifying that accepted.

Next, the operation of the conventional device will be described with reference to the drawings. In this example, device A1 and device B2
Will be issued at the same time, and the priority of the instructions at this time will always be assumed to be high on the device A1 side.

Referring to FIG. 2, first, the instruction buffer A
3 receives and holds the first command from the device A1 and outputs a wait command A signal 105. At the same time, the instruction buffer B4 receives and holds the first instruction from the device B2 and outputs the waiting instruction B signal 107.

The priority processing circuit 7 determines from the busy signal 114 whether the control circuit 8 is operating. The priority processing circuit 7 compares the waiting instruction A signal 105 with the waiting instruction B107 by the busy signal 114 "0" indicating that the control circuit 8 is not operating, and the device A1 issues the instruction according to the priority of the instruction. Accepts the first command, outputs the command / system number signal 111 and the reset A signal 106, and outputs the command buffer A3.
To reset.

In response to the command / system number signal 111, the control circuit 8 changes the busy signal 114 from "0" to "1",
The instruction is executed and the instruction acceptance notification A signal 112 is output to the device A1. In response to this signal 112, the instruction buffer A3
When the second instruction from the device A1 is stored and the execution of the instruction is completed, the busy signal 114 is set to "0" (empty state).

When the busy signal 114 is "1", the priority processing circuit 7 is stopped. However, when the busy signal 114 becomes "0", the priority processing circuit 7 compares the wait instruction A signal 105 and the wait instruction B signal 107 again. At this time, the second high-priority instruction issued by the device A1 is already in the instruction buffer A3.
Device A is set to
This is the second instruction issued by 1.

In this conventional instruction priority processing circuit, in a circuit shared by a plurality of systems, an instruction is issued from the system 1 and is being executed, and a system 2 issues a low priority instruction and is in a waiting state. At times, when the system 1 issues a high-priority instruction and enters a waiting state, the next instruction to be executed is the high-priority instruction issued by the system 1.

When this case is repeated, the low priority instruction issued by the system 2 is not executed and remains in the waiting state. Further, as the number of systems increases, the probability that an instruction will be in a waiting state for a long time increases.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an instruction interrupt priority control in an apparatus which receives an instruction from a plurality of systems and prioritizes the instruction so that an instruction of a certain system is not executed due to its low priority. It is to provide a processing device.

[0012]

An instruction interrupt priority processing apparatus according to the present invention includes an instruction buffer which holds an instruction issued by a system, outputs a waiting instruction signal and an instruction presence / absence signal, and resets an instruction after execution by a reset signal. A counter that outputs the interrupt signal when the waiting time of a waiting instruction is counted by inputting the instruction presence / absence signal from the instruction buffer and the given busy signal indicates that the busy signal stops operating and the busy signal Indicates that the instruction to be executed is selected with priority given to the interrupt signal from the counter as a higher priority than the type of the instruction and outputs the instruction system number signal and outputs the selected instruction to the system The priority processing circuit that outputs a reset signal to the instruction buffer and the command system number signal from this priority processing circuit Characterized in that it comprises a control circuit for a busy signal inactive to the running busy signal in response to the execution completion of the instruction being executed and active.

[0013]

An embodiment of the present invention will now be described in detail with reference to the drawings.

In one embodiment of the present invention, only two devices, A1 and B2, issue commands so that they can be directly compared with the above-mentioned prior art, and the devices A1 and B2 are the first.
It is assumed that the timing of issuing the second instruction is the same and the priority of the instruction is always high in the device A1.

Referring to FIG. 1, one embodiment of the present invention is
In addition to the device A1, the device B2, and the control circuit 3 which are the same constituent elements as those of the conventional technique, the device has the following features. The instruction buffer A3 holds the instruction from the device A1 and holds the instruction presence / absence A signal.
103 and the wait command A signal 105 are output, and the held contents are reset by the reset A signal 106 from the priority processing circuit 7.

The instruction buffer B4 holds the instruction from the device B2, outputs the instruction presence / absence B signal 104 and the waiting instruction B signal 106, and resets the held content by the reset B signal 108 from the priority processing circuit 7.

The counter A5 counts the waiting time of the instruction in the instruction buffer A3 based on the instruction presence / absence A signal 103 from the instruction buffer A3 and generates an interrupt A signal 109 at a predetermined time. The counter B6 counts the waiting time of the instruction in the instruction buffer B4 based on the instruction presence / absence B signal 104, and generates an interrupt B signal 110 at a predetermined time.

The priority processing circuit 7 confirms the "0" (empty state) of the busy signal 114 from the control circuit 8 and confirms the wait command A signal 10
5, the instruction to be executed is determined based on the wait instruction B signal 107, the interrupt A signal 109 from the counter A5, and the interrupt B signal 110 from the counter B6.

Next, the operation of the embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, first, the instruction buffer A3 holds the instruction A signal 101 issued by the device A1 as the first instruction, and outputs the wait instruction A signal 105 and the instruction presence / absence A signal 103. At the same time, device B2
The instruction buffer B4 holds the instruction B signal 102 issued by the instruction buffer B4 as the first instruction, and outputs the waiting instruction B signal 107 and the instruction presence / absence B signal 104.

The counter A5 to which the instruction presence / absence A signal 103 is input starts counting the waiting time of the instruction stored in the instruction buffer A3. The counter B6 to which the instruction presence / absence B signal 104 is input starts counting the waiting time of the instruction stored in the instruction buffer B4.

Next, the priority processing circuit 7 confirms "0" (empty state) of the busy signal 114 and inputs the wait instruction A signal 105, the wait instruction B signal 107, the interrupt A signal 109 and the interrupt B signal 110. Then, priority processing is performed to determine the instruction to be executed.

Here, as a factor for determining the priority level, the interrupt signal is the first and the instruction type is the second, and there are no interrupts from the counter A5 and the counter B6 at the present time. The priority processing circuit 7 selects the waiting instruction A signal 105, outputs the first instruction from the device A1 as the instruction / system number signal 111, and outputs the reset A signal 106. This reset A signal 10
In response to 6, the instruction buffer A3 resets the stored instruction.

The control circuit 8 to which the instruction / system number signal 111 is input shifts from the empty state to the instruction execution state, and the busy signal.
114 is output to the priority processing circuit 7 as "1". The priority processing circuit 7 suppresses the output of the next instruction to be executed by the "1" of the busy signal 114. Further, the control circuit 8 outputs the command acceptance notification A signal 112 to the device A1 in order to call the second command from the device A1.

The device A1 which receives the instruction acceptance notification A signal 112 issues the second instruction, and the instruction buffer A3 is in the waiting state for the second instruction. After that, the control circuit 8
When the instruction execution is completed, the busy signal 114 becomes "0" and becomes empty. According to the "0" state of the busy signal 114, the priority processing circuit 7 selects the instruction to be executed next.
If there is no interruption from each of the counters 5 and 6 at the time of this selection, the second instruction from the device A1 is executed, and the first instruction from the device B2 is not executed forever.

On the contrary, if there is an interrupt from the counter B6, the priority processing circuit 7 selects the wait instruction B signal 107 and selects the device B.
The first command of No. 2 is output as the command / system number signal 111, and the reset B signal is output to the command buffer B4.
Output to and reset.

The control circuit 8 which has received the command / system number signal 111 shifts to the command execution and sets the busy signal 111 to "1".
(In operation), the command acceptance notification B signal 113 is output to the device B2, and the second command is issued.

[0027]

According to the present invention, it is assumed that an instruction received from a plurality of systems will not be executed due to the low priority of the instruction of a certain system. In such a situation, the present invention is provided with a counter that counts the waiting time of an instruction for each system, and if an instruction with a waiting time longer than a certain limit occurs, an interrupt can be input to the priority processing circuit and executed first. It is characterized by doing so. As a result, the present invention has an effect that it is possible to eliminate a situation in which an instruction is kept waiting and is not executed.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional technique.

[Explanation of symbols]

 1 device A 2 device B 3 instruction buffer A 4 instruction buffer B 5 counter A 6 counter B 7 priority processing circuit 8 control circuit

Claims (1)

[Claims] 1. An instruction buffer for holding an instruction issued by a system, outputting a wait instruction signal and an instruction presence / absence signal, and resetting an instruction after execution by a reset signal, and an instruction presence / absence signal from these instruction buffers. A counter that counts the waiting time of the input and wait command and outputs an interrupt signal when it reaches a certain limit, and a counter that stops when the given busy signal indicates that it is operating and executes when the busy signal indicates that it is not operating. Priority processing of selecting an instruction to be executed, giving priority to an interrupt signal from the counter as a priority over the type of instruction, outputting an instruction system number signal, and outputting a reset signal to the instruction buffer of the system where the selected instruction is issued. The circuit and the instruction system number signal from this priority processing circuit are input and the busy signal is activated while the instruction is being executed. And a control circuit for making a busy signal inactive in response to completion of execution of the instruction in the interrupt priority processing apparatus.