JPH09134294A - Interruption control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set interruption priority to be appropriate and to execute a processing corresponding to the situation of interruption. SOLUTION: When respective interruption request signals become active while CPU 18 executes an interruption processing, a counter part 12 is counted up by one in accordance with the respective interruption request signals. When the interruption processing terminates, a priority judgment part 15 takes in respective counter values from the counter part 12 and takes in the setting priority of respective interruptions from an interruption priority setting register part 13. A priority judgment part 15 gives priority to interruption in accordance with the setting priority, but changes priority by considering the respective counter values, for example.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control circuit, and more particularly to an interrupt control circuit used in information equipment such as computer devices and information processing devices.

[0002]

2. Description of the Related Art Conventionally, as this type of interrupt control circuit, for example, an interrupt control circuit disclosed in Japanese Patent Laid-Open No. 4-373056 is known. In this interrupt control circuit, when determining the priority of the interrupt channel, the frequency or the waiting time of the interrupt request is determined using a counter or a timer, the interrupt priority is changed according to the determination result, and the central processing unit ( (CPU) usage efficiency is improved.

A conventional interrupt control circuit will now be outlined with reference to FIG.

The interrupt accepting unit 41 accepts interrupt requests from a plurality of channels, and instructs the interrupt request channels to the judging unit 43, the interrupt request issuing unit 44, and the interrupt vector issuing unit 45.

The counter section 42 is provided with a plurality of counters, and the number of interrupt requests for each channel is stored by the plurality of counters. The determination unit 43 is the interrupt reception unit 41
When an interrupt request is accepted from a plurality of channels at the same time, the counter value corresponding to each interrupt request channel is compared to identify the counter having the maximum value.

The interrupt request issuing unit 44 issues an interrupt request to the CPU 46 when the interrupt receiving unit 41 receives the interrupt request.

The interrupt vector issuing unit 45 issues an interrupt vector indicating the start address of the interrupt processing routine to be processed to the CPU 46.

As described above, when the interrupt accepting unit 41 receives interrupt requests from a plurality of channels at the same time, the determining unit 43 causes the interrupt vector issuing unit to prioritize the interrupt from the channel having the largest number of interrupt requests. Instruct 45.

[0009]

As described above, in the conventional interrupt control circuit, the interrupt priority changes depending on the number of interrupt requests (or interrupt waiting time) of the device (channel). Therefore, it is possible to perform interrupt processing according to the interrupt frequency.

However, depending on the information device, there is a device in which a fixed priority is set in the software processed by the CPU and interrupt processing is required. Therefore, there are cases where the interrupt control circuit described above cannot process the interrupt process as desired. In other words, even if the interrupt priority is changed by the interrupt control circuit, the fixed priority is set depending on the software, so that there is a problem that the interrupt processing cannot be appropriately processed as necessary.

It is an object of the present invention to provide an interrupt control circuit which can control the interrupt priority by the CPU or software processed by the CPU and can also set a fixed interrupt priority.

[0012]

According to the present invention, when there is an interrupt request from a plurality of devices, the priority of the interrupt request is judged and an interrupt instruction is given to the central processing unit according to the judgment result. In an interrupt control circuit for performing, a counter unit that counts the number of interrupt requests from each of the devices to obtain a count value, and an interrupt priority setting register in which the interrupt priority of each of the devices is set as a setting priority. And a priority determining means for issuing the interrupt instruction according to the magnitude of the count value when determining the priority based on the interrupt priority order set by the set priority. The circuit is obtained.

Further, according to the present invention, when there are interrupt requests from a plurality of devices, an interrupt control circuit for judging the priority of the interrupt requests and issuing an interrupt instruction to the central processing unit according to the judgment result. In the above, a timer unit that starts timing and measures a waiting time when there is the interrupt request from each of the devices, and an interrupt priority setting register unit in which the interrupt priority of each of the devices is set as a setting priority. And an interrupt control circuit having priority determining means for issuing the interrupt instruction according to the magnitude of the waiting time when priority is determined based on the interrupt priority order set by the set priority. Is obtained.

Further, according to the present invention, when there are interrupt requests from a plurality of devices, the interrupt control circuit for judging the priority of the interrupt requests and issuing an interrupt instruction to the central processing unit according to the judgment result. In the above, a counter unit that counts the number of times of the interrupt request from each of the devices to obtain a count value, and a timer unit that starts time counting and measures the waiting time when there is the interrupt request from each of the devices. , An interrupt priority setting register unit in which the interrupt priority of each of the devices is set as a set priority, and the magnitude of the count value when determining the priority based on the interrupt priority order set in the set priority. And an interrupt control circuit having priority determining means for issuing the interrupt instruction according to the waiting time.

[0015]

Next, the present invention will be described with reference to the drawings.

A first example of the interrupt control circuit according to the present invention will be described with reference to FIG.

The illustrated interrupt control circuit (interrupt controller) 11 includes a counter unit 12, an interrupt priority setting register unit 13, a setting register 14, and a priority determination unit 1.
5, an interrupt control unit 16, and a vector sending unit 17 are provided. The counter unit 12 includes n bits × m counters that store the number of interrupts from m devices (channels), and the interrupt priority setting register unit 13
As will be described later, is provided with m bits × k storage units for storing interrupt priorities of m devices set by the CPU 18. Further, a predetermined numerical value is set in the setting register 14 by the CPU 18, as described later.

In the CPU 18, each interrupt channel (a to d in FIG.
Note that a to d also represent interrupt request signals.
Interrupt register priority and setting register 14
Set a predetermined value to. In the illustrated example, the CPU 18
Sets interrupt channels a and c in the interrupt priority setting register unit 13 with the same priority and at the highest level,
Next, it is assumed that the priorities are set in the order of interrupt channel b and interrupt channel d. And the setting register 1
It is assumed that “4 (0100)” is set as 4 as a predetermined numerical value.

Now, an interrupt request signal b from a device connected to the interrupt control circuit (interrupt controller) 11.
It is assumed that has been input.

When the interrupt request signal b becomes active, the n-bit counter corresponding to the interrupt request signal b is incremented by 1 in the counter section 12.

When the priority determination unit 15 receives the interrupt request signal b, it fetches the counter value of each interrupt channel from the counter unit 12. Further, the priority determination unit 15 fetches the setting priority of each interrupt channel from the interrupt priority setting register unit 13 and fetches a predetermined numerical value (in this case, “4”) from the setting register 14 (in this case, each counter). Values of a, c, and d = 0, b = 1).

First, the priority determination unit 15 knows the priority of each channel based on the set priority. Next, the priority determination unit 15 checks the difference between the counter values. That is, the priority determination unit 15 determines that (ba) = 1, (ac) = 0, (a
-D) = 0, (b-c) = 1, (b-d) = 1, and (c-d) = 0. Since each of these differences is less than the predetermined numerical value “4”, the priority determination unit 15 determines that it is not necessary to change the set priority.

Next, the priority determination unit 15 checks the counter values of a and c having the highest priority according to the set priority, and a
Since both c and c are “0”, it is determined that the interrupt request is not made. Next, the priority determination unit 15 checks the value of the counter of b. Since b = 1, the priority determination unit 15 determines that an interrupt request is made, and sends the interrupt channel IDb of the interrupt channel b to the interrupt control unit 16 and the vector sending unit 17. At the same time, the priority determination unit 15 notifies the counter unit 11 to reset the counter value corresponding to the interrupt channel b to 0.

Upon receiving the interrupt channel IDb, the interrupt controller 16 sends an interrupt request signal to the CPU 18. When receiving the interrupt channel IDb, the vector sending unit 17 sends the value of the interrupt vector corresponding to the interrupt channel b to the CPU 18. As a result, the CPU 18 recognizes that the interrupt cycle has started and executes the interrupt.

Further, while the CPU 18 is performing the interrupt processing of the interrupt channel b. It is assumed that the interrupt request signal from another interrupt channel becomes active and is input to the interrupt controller 17.

Once the interrupt request signal of each interrupt channel becomes active, the counter section 11 increments the n-bit counter corresponding to each interrupt request signal by one.

When the interrupt processing of the interrupt channel b is completed and the CPU 18 notifies the interrupt control section 16 of the interrupt processing completion notification, the interrupt control section 16 interrupts the priority determination section 15 in response to the notification. Notify that the processing is completed.

At this time, it is assumed that the counter values of the counter section 12 are a = 3, b = 7, c = 10, and d = 1, respectively.

When the priority judging section 15 recognizes that the interrupt processing has been completed, it fetches the counter value of each interrupt channel from the counter section 12. Further, the priority determination unit 15 fetches the setting priority setting of each interrupt from the interrupt priority setting register unit 13 and sets the setting register 1
A predetermined numerical value “4” is fetched from 4.

First, the priority determination section 15 knows the priority of each channel based on the set priority. Next, the priority determination unit 15 determines (b−a) = 4, (c−a) = 7, (a−
d) = 2, (c−b) = 3, (b−d) = 6, and (c
-D) = 9 is calculated. As described above, the priority is a = c
Since>b> d are set in order, from the above difference,
Since (ba) is equal to or greater than the predetermined numerical value "4", it is determined that channel b has priority over channel a. On the other hand, (c-
b) = 3, the priority determination unit 15 determines that the channel b
Determines that channel c is not prioritized.

After that, the priority determination section 15 checks the counter values of a and c having the highest priority. Here, a =
3, c = 10, that is, (c−a) = 7, so that the priority determination unit 15 determines that the interrupt channel c has a larger number of interrupt requests than the interrupt channel a, and the urgency is high. to decide. Therefore, the priority determination unit 15
The interrupt channel IDc of the interrupt channel c is sent to the interrupt control unit 16 and the vector sending unit 17. At the same time, the priority determination unit 15 notifies the counter unit 12 to reset the counter value corresponding to the interrupt channel c to 0.

In response to the interrupt channel IDc, the interrupt controller 16 sends an interrupt request signal to the CPU 18. In response to the interrupt channel IDc, the vector sending unit 17 sends the value of the interrupt vector corresponding to the interrupt channel c to the CPU 18. This gives C
The PU 16 recognizes that the interrupt cycle has started, and executes the interrupt process.

In the example shown in FIG. 1, the counter 12 and the setting register 14 are used to change the setting priority, but a mode setting register (not shown) is provided instead of the setting register 14. May be. When the mode setting register is provided, the CPU 18 sets the mode in the mode register in advance. Then, for example, the mode (register value) shown in FIG. 2 is set in the mode setting register.

For example, if "10" is set in the mode setting register, the counter value is prioritized, and the interrupt priority is given to the channel having the largest counter value. When there are a plurality of the largest counter values, priority is given to the channel having the highest setting priority.

If the priority cannot be determined even in this way, the priority determination unit 15 gives the interrupt priority to a predetermined channel.

On the other hand, if "00" is set in the mode setting register, the interrupt priority is given to the channel having the highest setting priority. When there are a plurality of highest setting priorities, priority is given to a channel having a large counter value.

FIG. 3 is a block diagram showing a second example of the present invention. Referring to FIG. 3, the interrupt controller shown in FIG. 3 is different from the interrupt controller 11 shown in FIG. 1 in structure, and therefore, reference numeral 21 is used here. Specifically, the interrupt controller 21
However, the timer unit 22 is used instead of the counter unit 12, and the function of the priority determination unit is different from the function of the priority determination unit 15. Therefore, here, the reference numeral 23 is given to the priority determination unit. The rest of the configuration is the same as that of the interrupt controller 11.

The timer unit 22 includes m devices (channels).
Correspondingly, m timers are provided, and each timer starts timing when there is an interrupt request signal from the corresponding channel.

In this embodiment, the time count of the timer is used in place of the counter value described in FIG. 1, and the priority determination section 23 operates using the time count, except that the priority described in FIG. 1 is used. Since it is the same as the determination unit 15, the description thereof will be omitted. At this time, the set clock time is set in the setting register 14 as a predetermined numerical value, and the priority determination is performed according to the clock time of each timer as described with reference to FIG.

A mode setting register may be provided instead of the setting register 14. In this case,
Instead of the counter value shown in FIG. 2, the clock time is used as an element for determining the priority.

FIG. 4 is a block diagram showing a third example according to the present invention. Referring to FIG. 4, the interrupt controller shown in FIG. 4 is the interrupt controller 1 shown in FIGS.
The structure is different from that of 1 and 21, and therefore, 31 is used as a reference number here. Specifically, the interrupt controller 31 includes the counter unit 12 and the timer unit 22 described above. Since the function of the priority determination unit is different from that of the priority determination units 15 and 23, 32 is used as a reference number here. Further, the interrupt controller 31 has a mode setting register 33.

A mode (register value) is preset in the mode setting register 33 from the CPU 18. For example, one of the register values shown in FIG. 5 is set.

Now, the mode setting register 33 is set to "01".
If "1" is set, when performing the priority determination, the priority determination unit 32 first compares the values of the respective counters and gives the interrupt priority right to the channel having the largest counter value.
When there are a plurality of maximum counter values, the values of corresponding timers (measurement time) are compared and priority is given to the channel having the largest measurement time. When there are a plurality of maximum time counts, priority is given to the channel with the highest setting priority. If the priority cannot be determined even by the above-described method, the priority determination unit 32 gives the interrupt priority right to a predetermined channel.

As described above, since the priority determination unit 32 determines the priority according to the count value and the time count, the priority determination is performed using the frequency of interrupt requests and the length of interrupt waiting time. Therefore, it is possible to determine the priority according to the situation.

[0045]

As described above, according to the present invention, the CP
Since the interrupt priority is optimized by the function of setting the interrupt priority by U or software, it is possible to perform processing according to the status of the interrupt. Also,
By providing a counter unit that counts the interrupt request frequency and a timer unit that measures the interrupt waiting time, it is possible to more flexibly determine the priority according to the interrupt status and improve the CPU usage efficiency. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first example of an interrupt control circuit according to the present invention.

FIG. 2 is a diagram showing register values set in a mode setting register when the mode setting register is used in FIG.

FIG. 3 is a block diagram showing a second example of an interrupt control circuit according to the present invention.

FIG. 4 is a block diagram showing a third example of an interrupt control circuit according to the present invention.

5 is a diagram showing register values set in a mode setting register shown in FIG.

FIG. 6 is a block diagram showing a conventional interrupt control circuit.

[Explanation of symbols]

 11, 21, 31 Interrupt controller 12 Counter unit 13 Interrupt priority setting register unit 14 Setting register 15, 23, 32 Priority determination unit 16 Interrupt control unit 17 Vector sending unit 18 Central processing unit (CPU) 22 Timer unit 33 mode Configuration register

Claims (16)

[Claims] 1. When an interrupt request is issued from a plurality of devices, an interrupt control circuit that determines the priority of the interrupt request and issues an interrupt instruction to a central processing unit according to the determination result, A counter unit that counts the number of interrupt requests from the device to obtain a count value, an interrupt priority setting register unit in which the interrupt priority of each of the devices is set as a set priority, and a set by the set priority. An interrupt control circuit having priority determining means for issuing the interrupt instruction according to the magnitude of the count value when determining the priority based on the interrupt priority order. 2. The interrupt control circuit according to claim 1, wherein when the difference between the count values is equal to or more than a preset numerical value, the priority determining unit gives priority to a device having a large count value. An interrupt control circuit characterized in that it is determined to be a high order. 3. The interrupt control circuit according to claim 2, wherein the numerical value is given from the central processing unit to the priority determining means. 4. The interrupt control circuit according to claim 1, wherein the priority determining means is set with information for instructing which of the set priority and the counter value is to be prioritized. Interrupt control circuit. 5. The interrupt control circuit according to claim 4, wherein the information is given from the central processing unit to the priority determining means. 6. The interrupt control circuit according to claim 1, wherein the setting priority is set in the interrupt priority setting register section from the central processing unit. Interrupt control circuit. 7. An interrupt control circuit which, when there are interrupt requests from a plurality of devices, judges the priority of the interrupt requests and gives an interrupt instruction to a central processing unit in accordance with the judgment result. A timer unit that starts timing and measures the waiting time when there is an interrupt request from the device, an interrupt priority setting register unit in which the interrupt priority of each of the devices is set as a setting priority, and the setting priority. 2. An interrupt control circuit, comprising: priority determining means for issuing the interrupt instruction according to the magnitude of the waiting time when determining the priority based on the interrupt priority order set in 1. 8. The interrupt control circuit according to claim 7, wherein when the difference between the waiting times is equal to or greater than a preset time value, the priority determining unit prioritizes the devices having the long waiting time. The interrupt control circuit is characterized in that it is determined that is higher. 9. The interrupt control circuit according to claim 8, wherein the time value is given from the central processing unit to the priority determining means. 10. The interrupt control circuit according to claim 7, wherein the priority determining means is set with information instructing which of the set priority and the waiting time is to be prioritized. Interrupt control circuit. 11. The interrupt control circuit according to claim 10, wherein the information is given from the central processing unit to the priority determining means. 12. The interrupt control circuit according to claim 7, wherein the setting priority is set in the interrupt priority setting register section from the central processing unit. Interrupt control circuit. 13. An interrupt control circuit which, when there are interrupt requests from a plurality of devices, judges the priority of the interrupt requests and gives an interrupt instruction to a central processing unit according to the judgment result. A counter unit that counts the number of interrupt requests from
A timer unit that starts a timing when there is the interrupt request from each of the devices and measures a waiting time; an interrupt priority setting register unit in which the interrupt priority of each of the devices is set as a setting priority; An interrupt characterized by having priority determining means for issuing the interrupt instruction in accordance with the size of the count value and the waiting time when determining the priority based on the interrupt priority order set by the set priority. Control circuit. 14. The interrupt control circuit according to claim 13, wherein the priority determining means is set with information indicating a priority order among the set priority, the count value and the waiting time. An interrupt control circuit characterized in that 15. The interrupt control circuit according to claim 13, wherein the information is given from the central processing unit to the priority determining means. 16. The interrupt control circuit according to claim 13, wherein the setting priority is set in the interrupt priority setting register section from the central processing unit. Interrupt control circuit.