JP2884764B2 - Signal processor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processor capable of processing two signals having different sampling intervals, such as a PCM signal and a digital audio signal, in parallel.

(Prior Art) Conventionally, as a method of processing signals of a plurality of sampling rates in parallel by a signal processor or the like, there are 1) a method using a plurality of interrupts and 2) a program control method.

In the method using a plurality of interrupts, an interrupt signal with a priority is assigned to each process having a different sampling rate, and the process at each sampling rate is executed by the interrupt signal. Since each sampling rate is different, an interrupt that activates processing at a different sampling rate may be input during execution of processing at one rate. In this case, if the priority of the input interrupt is high, the currently executing process is interrupted, the process corresponding to the interrupt signal is executed, and when the process is completed, the process before the interrupt input is resumed. Also,
If the priority is low, the interrupt process is started after the process currently being executed ends. In this manner, processes having different sampling rates can be executed in parallel.

On the other hand, in the method based on program control, multirate processing is realized by repeatedly executing processing with different sampling rates according to the sampling rate in one program. For example, when the ratio of the sampling rates of the two processes A and B is 2: 3, this can be realized by repeating a program that repeats A twice and B three times at half the sampling rate of A.

(Problems to be Solved by the Invention) However, in the method using a plurality of interrupts, there is a large overhead such as evacuation of the internal state of the processor due to the interruption of the processing due to the high-priority interrupt, and the real-time processing with a strong time constraint. Has been required to reduce the processing time. In particular, in a processor employing pipeline processing for speeding up, the pipeline is interrupted by an interrupt, so that the computation efficiency is greatly deteriorated.

On the other hand, the method based on the program control is limited to the case where m and n can be represented by integers when the ratio of two different sampling rates is m: n. Even when each of them can be represented by an integer, when the least common multiple of m and n is large, there is a practical problem because the program, processing delay, required memory and the like become large.

An object of the present invention is to provide a signal processor which can be efficiently realized on a program even when there are a plurality of processes in which a ratio of two different sampling rates cannot be represented by a simple integer ratio.

(Means for Solving the Problems) A signal processor according to the present invention includes: a frequency dividing circuit that divides a first interrupt input input at a first sampling interval to generate a frequency dividing interrupt signal; A counter circuit that uses the frequency-divided interrupt signal as a reset signal and counts the number of second interrupt inputs that are input at a second sampling interval within the reset signal interval, and outputs the counter circuit when the reset signal is input. A judgment circuit for judging whether or not the number coincides with a predetermined number; and 2 stored in advance according to an output of the judgment circuit.
A program selection circuit for selecting one of the two programs; a first internal input buffer and a first internal output buffer;
A first input / output circuit for storing an input signal of the first internal input buffer and outputting an output signal stored in the first internal output buffer; a second internal input buffer;
A second input signal is stored in the second internal input buffer in synchronization with the second interrupt input, and a second output signal stored in the second internal output buffer is output. An input / output circuit and a signal sequence stored in the first input / output circuit or the second input / output circuit are input, a program selected by the program selection circuit is executed, and an output signal sequence is output to the first input / output circuit. And the program execution unit stored in the second input / output circuit.

(Operation) The principle of the present invention will be described below. When the ratio of the input / output sampling rate in the system to be realized is expressed as a: m, when a is a non-integer with respect to an integer value m, n <a <n +
The integer that becomes 1 is n. At this time, it is clear that the number of samples input while outputting only m samples is n or n + 1. Therefore, a program for the case where the ratio of the input and output sampling rates is n: m and a program for the case where n + 1: m are prepared in advance, and the number of input samples input while outputting m samples is n. Or n + 1
By selecting and executing one of the two programs depending on whether the input / output sampling rate is equal to or less than the above, it is possible to realize a system in which the input / output sampling rate ratio is a: m.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention. In this embodiment, a first interrupt input terminal 1, a frequency divider 2, a second interrupt input terminal 3, a counter circuit 4, and a decision circuit 5 are shown. , Program selection circuit 6, first input / output circuit 7, first
Signal input terminal 8, first signal output terminal 9, second input / output circuit 10, second signal input terminal 11, second signal output terminal
12 and a program execution unit 13.

The frequency dividing circuit 2 divides the first interrupt input 101 by a predetermined number and outputs a frequency-divided interrupt signal 102. For example, assuming that the number of frequency divisions is M (M is an integer), the frequency dividing circuit 2 outputs the frequency-divided interrupt output once each time the first interrupt input 101 is input M times. The counter circuit 4 counts the number of the second interrupt inputs 103 input at adjacent input intervals of the divided interrupt signal 102, and outputs the divided interrupt signal 102 as a reset signal and a second interrupt input. This can be realized by an up counter using 103 as a counter input. The judgment circuit 5 outputs the output 104 of the counter circuit 4 in response to the divided interrupt signal 102 input.
Is equal to a predetermined number, and a determination signal 105
Is output. The program selection circuit 6 is a program
One of the types of programs is selected and output according to the determination signal 105. The first input / output circuit 7 has a built-in internal input buffer and an internal output buffer.
The signal 108 is input from the signal input terminal 8 according to 1 and stored in the internal input buffer. The signal 109 is read from the internal output buffer and output from the signal terminal 9. The second input / output circuit 10 also has a built-in internal input buffer and an internal output buffer.
And stores it in the internal input buffer, reads out the signal 112 from the internal output buffer, and outputs it to the signal output terminal 12.
The program execution unit 13 reads the input signal sequence from the internal buffers of the first input / output circuit 7 and the second input / output circuit 10 in accordance with the program selected by the program selection circuit 6, performs processing, and then outputs the output signal sequence. Is stored in the internal buffers of the first input / output circuit 7 and the second input / output circuit 10.

In the signal processor of the embodiment, the ratio between the sampling rate of the input signal and the sampling rate of the output signal is R, and R
Against Is established. At this time, the first interrupt input 101 is frequency-divided by M in the frequency dividing circuit 2 and
The number of the second interrupt inputs 103 input during the divided interrupt interval is counted. This number is N (N is an integer)
Or N + 1. Therefore, when the interrupt signal 102 divided by M is input, the determination circuit 5 determines whether the output 104 of the counter circuit 4 is N and outputs a determination signal 105. At the same time, the counter circuit 4 is set to 0.
Reset. Then, the program selection circuit 6 selects a program as follows and causes the program execution unit 13 to execute the program. First, when the determination signal 105 indicates N sample input, M samples are input to the internal input buffer of the first input / output circuit 7 and N samples are input to the internal input buffer of the second input / output circuit 10. Therefore, the program selection circuit 6 selects a program that repeats the process corresponding to the first interrupt process M times and repeats the process corresponding to the second interrupt process N times, and causes the program execution unit 13 to process the selected program. On the other hand, when the judgment signal 105 indicates N + 1 sample input, the built-in buffer of the second input / output circuit 10
Since +1 sample has been input, the program selection circuit 6 selects a program that repeats the process corresponding to the first interrupt process M times and the process corresponding to the second interrupt process N + 1 times, and selects the program execution unit 13 To process.

(Effect of the Invention) As described above, according to the present invention, parallel signal processing is efficiently realized by a program even when there are two different sampling rate processes that cannot be expressed by a simple integer ratio. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing the configuration of one embodiment of the present invention. 1... First interrupt input terminal, 2... Frequency divider circuit, 3.
... Second interrupt input terminal, 4 ... Counter circuit, 5 ...
... Determination circuit, 6... Program selection circuit, 7... First input / output circuit, 8... First signal input terminal, 9... First signal output terminal, 10. , 11... Second signal input terminal, 12... Second signal output terminal, 13.

Claims (1)

(57) [Claims] A frequency divider circuit for dividing a first interrupt input inputted at a first sampling interval to generate a frequency-divided interrupt signal, and using the frequency-divided interrupt signal as a reset signal, A counter circuit for counting the number of second interrupt inputs input at a second sampling interval within the signal interval, and determining whether an output of the counter circuit at the time of inputting the reset signal matches a predetermined number. A determination circuit, a program selection circuit for selecting one of two programs stored in advance in accordance with an output of the determination circuit, a first internal input buffer and a first internal output buffer A first input / output circuit that stores a first input signal in the first internal input buffer in synchronization with the first interrupt input and outputs an output signal stored in the first internal output buffer; 2 internal input bus And a second internal output buffer, and stores a second input signal in the second internal input buffer in synchronization with the second interrupt input, and outputs an output signal stored in the second internal output buffer. A second input / output circuit and a signal sequence stored in the first input / output circuit or the second input / output circuit, execute a program selected by the program selection circuit, and output a signal sequence. And a program execution unit that stores the program in the first input / output circuit or the second input / output circuit.