JPH1115800A - Multiprocessor load uniformizing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To uniformize load based on measuring correctly the load state of each multiprocessor. SOLUTION: Each processor is provided with a time measuring part 2 that measures current time, calculates the difference between time when interrupt is received and time when the processing of the interrupt task is completed, makes it the time that is taken from the receiving of the interrupt till the processing completion of the interrupt task and assumes that the time is in proportion to the load of a processor. A CPU 1 controls an interrupt delaying part 3 in accordance with the size of load. With this, the receiving of interrupt is limited and load is uniformized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load equalizing apparatus for preventing a load from being concentrated on a specific processor in a loosely-coupled multiprocessor.

[0002]

2. Description of the Related Art In a device having a loosely coupled multiprocessor configuration, Japanese Patent Laid-Open Publication No. Hei 7-244649 discloses a conventional technique for dispersing the load by preventing interrupt processing from being concentrated on a specific processor. The description will be described.

FIG. 7 is a block diagram showing a configuration of a conventional load distribution device.

In the CPU board 70, reference numeral 75 denotes a queue counter for counting interrupt factor processing tasks;
6 is a CPU for generating an interrupt signal according to the queue counter value.
An interrupt transmission control unit that controls the time or the number of transmissions to 71. The queue counter 75 changes the CPU 71 according to the occurrence or disappearance of the queue of the interrupt factor processing task.
Is controlled to count up or count down. The interrupt transmission control unit 76 controls the interrupt signal input from the interrupt bus 79 to limit the time or the number of interrupt signals transmitted to the CPU 71 in accordance with the count value of the queue counter 75.

[0005] In FIG. 7, a queue counter 75
The CPU 71 activates the interrupt processing, counts up when the interrupt factor processing task is loaded in the queue, and controls to count down when the interrupt factor processing task is activated and the processing is completed. Accordingly, the number of queues currently loaded is counted in the queue counter 75.

The interrupt transmission control unit 76 controls the number or time of the interrupt signal input from the interrupt bus 79 to be transmitted to the CPU 71 in accordance with the value of the queue counter 75. That is, as the value of the queue counter 75 increases, the delay time of the interrupt to be notified to the CPU 71 is increased, and the time required for activating the interrupt process is increased to reduce the queue.

In this manner, as the number of interrupt queues increases, the acceptance of interrupts is restricted, and the concentration of interrupts can be prevented.

[0008]

The above prior art has the following problems.

A first problem is that in the prior art, the acceptance of interrupts is controlled by the accumulated number of interrupt cause tasks. However, the interrupt processing tasks vary in processing time, some of which have long processing times and some of which have short processing times, and the load state cannot be accurately grasped only by the number of tasks.

It is important to limit the number of interrupts accepted according to the load state, and it is necessary to take into account the task processing time.

[0011] The reason is that the time from the occurrence of an interrupt to the completion of the interrupt processing increases in proportion to the load on the CPU board. In a device using a CPU board, if the time from the occurrence of an interrupt to the completion of interrupt processing becomes longer than a certain value, there is a possibility that the function as the device may not be achieved, and this is serious.

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, an object of the present invention is to provide a multiprocessor with an equalizing device which distributes loads by allocating interrupts to respective CPU boards so that all interrupts are completed within a predetermined time. To provide.

[0013]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an apparatus having a loosely coupled multiprocessor configuration in which a plurality of CPU boards each having a CPU mounted thereon are connected in parallel. CPU, comprising: a time measuring unit for measuring the delay time; and an interrupt delay unit that can vary a delay amount with respect to an interrupt input to each CPU board.
Can read the current time from the time measurement unit,
The PU is a multi-processor load equalizing device characterized in that the delay amount of the interrupt delay unit can be controlled.

When the interrupt is accepted, the interrupt information is accumulated in the interrupt queue, and at the same time, the time is stored, and the difference between the time when the interrupt task is completed and the time when the interrupt task is accumulated in the interrupt queue is stored. Is set as the load state of the CPU board, and the amount of delay of the interrupt signal to the CPU board is set according to the load state of the CPU board to delay the interrupt signal to the CPU. (Operation) When an interrupt occurs, the interrupt is input to all CPU boards. The CPU board holds the interrupt internally and issues a common bus acquisition request to respond to the interrupt when the currently executing instruction is completed. The CPU board that has acquired the bus executes the interrupt response bus cycle, reads the interrupt vector from the interrupt source,
Identify the interrupt source. CPU that could not get the bus
The board acquires the bus later, but for the bus cycle of the interrupt response at that time, since the interrupt source has already sent the vector, it makes a bus error without outputting the vector. The CPU board in which a bus error has occurred in the interrupt response bus cycle invalidates the interrupt.

The CPU board that has received the vector enters an interrupt acceptance process, saves the registers, reads the contents of the interrupt request from the interrupt source, and accumulates the interrupt request in the interrupt queue. Next, the current time is read from the time measuring unit and stored in the queue as additional information of the interrupt queue. The above is the processing when an interrupt occurs.

The CPU board always monitors the interrupt queue. If interrupts are accumulated in the interrupt queue, the CPU board reads the interrupt information from the lowest queue and transfers the process to the interrupt task. The interrupt task performs a process based on the interrupt information of the queue. The time at which the processing of the interrupt task is completed is read from the time measuring unit, and the difference from the interrupt reception time stored in the queue is calculated.

If the calculated result exceeds the predetermined upper limit time, it is determined that the load on the CPU board is large, and the interrupt delay of the interrupt delay unit is changed so as to increase. If the time is shorter than the predetermined lower limit time, the interrupt delay time of the interrupt delay unit is changed to be shorter. With these operations, when the time from the occurrence of an interrupt to the completion of the task processing of the interrupt is long, that is, when the load on the CPU board is high, the delay time of the interrupt can be increased, the acceptance of interrupts can be reduced, and the load on the multiprocessor can be reduced. Can be made uniform.

[0018]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a load equalizing apparatus according to an embodiment of the present invention.

The CPU board 10 has a CPU 1 and a memory 5.
A time measuring unit 2 for measuring the current time, a bus arbitration unit 4 for allowing the CPU 1 to access the external common bus 6,
Interrupt delay unit 3 for inputting an interrupt to CPU 1
And constitutes a multiprocessor with other CPU boards. The interrupt is input commonly to all CPU boards through the interrupt bus 7 and is input to the CPU 1 through the interrupt delay unit 3. The interrupt delay unit 3 is set by the CPU 1 for the amount of interrupt delay. CP
U1 performs processing by reading / writing the memory 5, and the CPU 1 can read the current time from the time measuring unit 2.

An outline of an embodiment of the present invention will be described.

When an interrupt is input to the CPU board, the interrupt signal is input to the CPU 1 after being delayed by the interrupt delay unit 3. The CPU 1 suspends the interrupt, and issues an interrupt response to the I / O of the interrupt source using the common bus 6 when the current instruction is completed. The IO at the interrupt source returns an interrupt vector to the CPU board 10 in response to the interrupt response. CPU that received the interrupt response
1 saves the register, reads the interrupt information from the IO of the interrupt source, and accumulates the interrupt information in the memory 5 as an interrupt queue. The time at this time is read from the time measuring unit 2 and stored in the interrupt queue as additional information of the interrupt information.

The CPU 1 always monitors the interrupt queue,
If the interrupt information has been accumulated in the interrupt queue, the interrupt information is read from the interrupt queue and the interrupt task is started. Performs interrupt processing based on the interrupt information in the interrupt queue, reads the time of completion from the time measuring unit 2, calculates the difference from the time stored at the time of receiving the interrupt, and calculates the time from the reception of the interrupt to the end of the interrupt task. Ask.

FIG. 5 is a conceptual diagram in the case where the time from the acceptance of the interrupt to the end of the interrupt task is short. After accepting the interrupt of A, the interrupt task of A is activated and the interrupt task is completed, the next interrupt of B is accepted, and after the interrupt task of B is completed, the next interrupt acceptance C is performed. In this case, there is no delay in the processing of the interrupt.

FIG. 6 shows an example in which there is a delay in interrupt processing due to a long processing time of the interrupt task. This is a case where the interrupt acceptance D is performed, the interrupt task processing D is started, and the next interrupt acceptance E is present before the processing of the interrupt task D is completed. In this case, the interrupt task processing E waits until the interrupt task processing D is completed, and the time from the reception of the interrupt E to the completion of the interrupt task processing E increases. Further, the interrupt acceptance process F is waited until the interrupt task process E is completed, and then the interrupt task process F is activated, so that the time from the acceptance of the interrupt to the completion of the interrupt task is further increased. By measuring the time from interrupt acceptance to completion of interrupt task processing in this way, the CPU
The load on the board can be known accurately.

The relationship between the time from the reception of the interrupt to the completion of the interrupt task processing and the delay time of the interrupt delay unit are set in advance, and the interrupt delay time is determined. By setting the obtained interrupt delay time in the interrupt delay unit, the delay time of the interrupt is controlled and the acceptance of the interrupt is limited.

A specific description will be given using numerical values.
The processing time of the interrupt task processed by the board 10 is 0.
Assume that it varies from 1 mS to 10 mS. It is assumed that the maximum value of the number of stacked interrupt queues is 64.

In this case, after the interruption is accepted,
Maximum time to complete interrupt task is 10ms
x64 = 640 ms. Since the time measurement unit 2 needs to measure the time longer than this time, here, 4096 counts in 1 mS units, that is, the maximum measurement time is set to 4.096S.
And The time measurement unit is 0 if it counts 4.096S
Returning to the count is always repeated.

The maximum value of the delay time of the interrupt processing allowed in the system controlled by the multiprocessor is set to 0.
Assume 5S.

Next, an interrupt delay unit constituting an embodiment of the present invention will be described. FIG. 2 is a diagram showing a circuit configuration of the interrupt delay unit.

As shown in FIG. 2, the interrupt delay unit 3 comprises a shift register 31, a selector 32 for selecting an output of the shift register, and a latch 33 for storing a selected value in the selector 32. The delay amount of the delay unit 3 can be set in eight stages. The delay amount of the interrupt delay unit must be changed by setting the probability of interrupt acceptance.
It must be longer than one instruction execution time. CPU1
Is assumed to be 0.6 .mu.S, the delay unit of the interrupt delay unit 3 is 2 .mu.S. That is, the delay time of the interrupt delay unit is 0 μS to a maximum of 14 μS in 2 μS units.
(See FIG. 4B).

The process of accepting an interrupt will be described with reference to the drawings.

FIG. 3A is a flowchart of the interrupt acceptance process, and FIG. 3B is an interrupt queue table.

When the interrupt source IO generates an interrupt, the interrupt signal is input to the interrupt delay units 3 of all CPU boards through the interrupt bus 7. Since the reset terminal of the shift register 31 of the interrupt delay unit 3 goes low, the shift terminal 31 starts shifting the high level of the D terminal. Latch 3 of interrupt delay unit 3
3 is “010”, the shift register 31 Q
The value of B is transmitted to CPU1. In this case, the interrupt signal is input to the CPU 1 with a delay of 4 μS (step 1).

The interrupt input to the CPU 1 is held internally, and a bus request is issued to the bus arbitration unit 4 to issue an interrupt response when the currently executed instruction is completed. If the bus can be acquired, an interrupt response bus cycle is sent to the common bus 6, and the interrupt vector is read from the interrupt source IO (step 2).

The CPU 1 receiving the vector saves the stack of the register (step 3), reads the interrupt information from the interrupt source IO, and accumulates the interrupt information in the interrupt queue (step 4). Since the interrupt acceptance processing has been completed, the time at this time is read from the time measuring unit 2 (step 5). It is assumed that the time at that time, that is, the count value is 1000. This count value 1
000 is stored as a part of the information accumulated in the queue (step 6).

Next, the processing of the interrupt task will be described with reference to the drawings.

FIG. 4A is a flowchart of the interrupt task process, and FIG. 4B is a table showing the relationship between the time from the reception of the interrupt to the completion of the interrupt task and the delay amount of the interrupt delay unit.

The CPU 1 always monitors the state of the interrupt queue. If there is interrupt information accumulated in the interrupt queue, the CPU 1 starts processing from the information in the lowest interrupt queue, that is, the interrupt caught in the past. Activate an interrupt task based on the interrupt information in the interrupt queue,
Task processing is performed (step 8). When the task processing is completed, the counter of the time measuring unit 2 is read to measure the time from the acceptance of the interrupt, and the count value 1
Assume that you read 045. The difference 45 between the interrupt reception time stored in the interrupt queue and 1000 is obtained, and it is known that the time from the reception of the interrupt to the completion of the interrupt task took 45 ms.

A table (see FIG. 4B) indicating the relationship between the time from the acceptance of the interrupt to the completion of the interrupt task and the delay amount of the interrupt delay unit 3 is set in advance.
Time from interrupt acceptance to interrupt task completion, 4
5mS is equivalent to the delay amount "001", and C
PU1 sets "001" in the latch 33 of the interrupt delay unit 3 (step 9).

If the counter value of the time measuring unit 2 at the time of interrupt acceptance is 4040, and the counter value of the time measuring unit 2 at the time of completion of the interrupt task is 0020, the counter value of the time measuring unit at the time of accepting the interrupt is Is large, it is determined that the counter has made one round, and the value of 76 can be obtained by subtracting 4040 from 4096 and adding the difference and 0020, so that in any case, the time from the acceptance of the interrupt to the completion of the interrupt task can be obtained. it can.

Next, as another embodiment, when there are a plurality of interrupt levels, the execution time of the interrupt task can be predicted to some extent based on the interrupt levels.

For example, when there are interrupt levels 1 and 2, the interrupt task processing time of interrupt level 1 is 1 m
S, if the interrupt task processing time of the interrupt level 2 is 10 mS, when the CPU monitors the interrupt queue, a value obtained by multiplying the number accumulated in the interrupt queue of the interrupt level 1 by 1 mS and the interrupt By adding a value obtained by multiplying the number stored in the level 2 interrupt queue by 10 mS, the maximum time from the acceptance of the interrupt to the completion of the interrupt task processing at the present time can be predicted.
In this case, the time measurement unit becomes unnecessary. If the time from the acceptance of the interrupt to the completion of the interrupt task is known, the amount of delay of the interrupt delay unit can be set from a table showing the relationship between the time and the delay time of the interrupt delay unit.

As another embodiment, a hard timer tied to an interrupt queue is provided, and when an interrupt is accepted, a timer corresponding to the stacked interrupt queue is started and an interrupt task is completed. The load on the CPU board can be measured by reading the timer corresponding to, and setting the value as the time from the acceptance of the interrupt to the completion of the interrupt task.

[0045]

The first effect is that when the load on the CPU board is increased, the interrupt processing time is lengthened to affect the system. The longer processing time is due to the longer waiting time before starting the interrupt processing task.
By measuring the time from the acceptance of the interrupt to the completion of the interrupt task processing, the CPU board load can be accurately measured.

By accurately measuring the load, the probability of receiving an interrupt can be finely controlled and the load can be made uniform.

The reason is that the time at which the interrupt is accepted is stored as additional information in the interrupt queue, and the difference between the time at which the interrupt task processing is completed and the time stored in the interrupt queue is determined. The time until completion can be measured, and the load on the CPU board can be accurately known. The interrupt input circuit has an interrupt delay unit, and the delay time of the interrupt can be precisely controlled according to the load, so that the load on the CPU board can be equalized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a load equalizing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a circuit configuration of an interrupt delay unit;

FIG. 3A is a flowchart of an interrupt acceptance process;
(B) Interrupt queue table

FIG. 4A is a flowchart of interrupt task processing;
(B) A table showing the relationship between the time from the acceptance of an interrupt to the completion of the interrupt task and the delay amount of the interrupt delay unit

FIG. 5 is a timing chart of interrupt processing with a light load;

FIG. 6 is a timing chart of heavy interrupt processing.

FIG. 7 is a block diagram showing a configuration of a conventional load distribution device.

[Explanation of symbols]

 1 CPU 2 Time measurement unit 3 Interrupt delay unit 31 Shift register 32 Selector 33 Latch 4 Bus arbitration unit 5 Memory 6 Common bus 7 Interrupt bus 10 CPU board 70 CPU board 71 CPU 72 Decoder 73 Bus arbitration unit 74 Buffer 75 Queue counter 76 Interrupt transmission control unit 77 Common bus 78 Arbitration bus 79 Interrupt bus

Claims (3)

[Claims] An apparatus having a loosely coupled multiprocessor configuration in which a plurality of CPU boards each having a CPU mounted thereon are connected in parallel, a time measuring unit for measuring the current time on each CPU board, and an interrupt to each CPU board. An interrupt delay unit capable of changing a delay amount with respect to an input;
Can read the current time from the time measurement unit,
An apparatus for equalizing a load of a multiprocessor, wherein a PU can control a delay amount of an interrupt delay unit. 2. When an interrupt is accepted, interrupt information is accumulated in an interrupt queue, and at the same time, a time is stored, and the difference between the time when the interrupt task is completed and the time when the interrupt task is accumulated in the interrupt queue. To C
2. The apparatus for equalizing loads of a multiprocessor according to claim 1, wherein the state of the loads on the PU boards is set. 3. The CPU according to the load state of the CPU board.
3. The apparatus according to claim 2, wherein a delay amount of the interrupt signal to the board is set to delay the interrupt signal to the CPU.