JPH01280336A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01280336A JPH01280336A JP63110988A JP11098888A JPH01280336A JP H01280336 A JPH01280336 A JP H01280336A JP 63110988 A JP63110988 A JP 63110988A JP 11098888 A JP11098888 A JP 11098888A JP H01280336 A JPH01280336 A JP H01280336A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystalline silicon
- oxide film
- silicon layer
- phosphorus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 39
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 18
- 239000011574 phosphorus Substances 0.000 claims abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 6
- 230000003647 oxidation Effects 0.000 claims abstract description 4
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 4
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- QVMHUALAQYRRBM-UHFFFAOYSA-N [P].[P] Chemical compound [P].[P] QVMHUALAQYRRBM-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法、特にＣＣＤ。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of manufacturing a semiconductor device, particularly a CCD.
Ｄ−ＲＡＭ等のリン（Ｐ）を含む２層の多結晶シリコン
・ゲート電極を有する半導体装置の製造方法に関する。The present invention relates to a method of manufacturing a semiconductor device such as a D-RAM having a two-layer polycrystalline silicon gate electrode containing phosphorus (P).
第３図（ａ）〜（ｃ）はリン（Ｐ）を含む２層の多結晶
シリコン・ゲート電極を有する半導体装置の従来の製造
方法を示す工程図で、ゲート酸化膜の形成から第２層目
の多結晶シリコン層のパターンを形成するまでは、第３
図（ａ）〜（ｃ）に示される順序で製造される。すなわ
ち、まず第３図（ａ）に示すように、半導体基板１の一
生面の所定域にＭＯＳトランジスタのゲート酸化膜およ
び容址を構成する薄いシリコン酸化膜２を形成し、この
上にリン（Ｐ）を拡散した多結晶シリコン層３のパター
ンを形成する。次に第３図（ｂ）に示すように、このリ
ン（Ｐ）を含む多結晶シリコン層３をマスクにしてシリ
コン酸化膜２を選択的にエツチングする。ついで、第３
図（Ｃ）に示すように、第２のゲート酸化膜となるシリ
コン酸化膜４を形成し、再びリン（Ｐ）を拡散した第２
層目の多結晶シリコン層５のパターンを形成するもので
ある。FIGS. 3(a) to 3(c) are process diagrams showing a conventional manufacturing method of a semiconductor device having a two-layer polycrystalline silicon gate electrode containing phosphorus (P), from the formation of a gate oxide film to the second layer Until forming the pattern of the polycrystalline silicon layer, the third
They are manufactured in the order shown in Figures (a) to (c). That is, as shown in FIG. 3(a), first, a thin silicon oxide film 2, which constitutes the gate oxide film and the cavity of the MOS transistor, is formed in a predetermined area on the whole surface of the semiconductor substrate 1, and then phosphorus (phosphorus) is formed on this film. A pattern of a polycrystalline silicon layer 3 in which P) is diffused is formed. Next, as shown in FIG. 3(b), the silicon oxide film 2 is selectively etched using the polycrystalline silicon layer 3 containing phosphorus (P) as a mask. Then, the third
As shown in FIG.
This is to form a pattern for the second polycrystalline silicon layer 5.
このように、上述した従来の半導体装置の製造方法は、
第１層目の多結晶シリコン層のパターンを形成した後、
それをマスクとして露呈されているシリコン酸化膜はす
べてエツチング除去される。従って、次に第１層目の多
結晶シリコン層の表面を再度酸化するとき、第１層目の
多結晶シリコンに拡散しであるリン（Ｐ）が外に向かっ
て拡散し露呈している基板にまで拡散することがあり、
これにより特性異常を引き起こすという欠点が生じる。In this way, the conventional semiconductor device manufacturing method described above is
After forming the pattern of the first polycrystalline silicon layer,
Using this as a mask, all of the exposed silicon oxide film is removed by etching. Therefore, when the surface of the first polycrystalline silicon layer is oxidized again, the phosphorus (P) that has diffused into the first polycrystalline silicon layer diffuses outward, leaving the exposed substrate exposed. It can spread to
This has the disadvantage of causing characteristic abnormalities.
本発明の目的は、上記の情況に鑑み、リン（ｐ）を含む
２層の多結晶シリコン・ゲート電極を形成する除虫じる
第１層目の多結晶シリコン層からの外向きリン（Ｐ）拡
散を防止した半導体装置の製造方法を提供することであ
る。In view of the above circumstances, an object of the present invention is to remove outward phosphorus (P) from the first polycrystalline silicon layer forming a two-layer polycrystalline silicon gate electrode containing phosphorus (P). ) An object of the present invention is to provide a method for manufacturing a semiconductor device that prevents diffusion.
本発明によれば、半導体装置の製造方法は、−導電型の
半導体基板上の所定域にゲート酸化膜を形成する工程と
、前記ゲート酸化膜上にリンを含む第１層目の多結晶シ
リコン層をパターン形成する工程と、前記第１Ｎ目の多
結晶シリコン層に覆われることなく露呈する前記ゲート
酸化膜をある程度の厚さを残してエツチング除去する工
程と、前記第１層目の多結晶シリコン層の表゛面を再度
酸化する工程と、前記酸化工程で形成される多結晶シリ
コン酸化膜上に一部を延在させて第２層目の多結晶シリ
コン層を形成する工程とを含んで構成される。According to the present invention, a method for manufacturing a semiconductor device includes the steps of: forming a gate oxide film in a predetermined area on a -conductivity type semiconductor substrate; and forming a first layer of polycrystalline silicon containing phosphorus on the gate oxide film. a step of patterning the first polycrystalline silicon layer; a step of etching away the gate oxide film that is exposed without being covered by the first Nth polycrystalline silicon layer, leaving a certain thickness; The method includes a step of oxidizing the surface of the silicon layer again, and a step of forming a second polycrystalline silicon layer by extending a portion over the polycrystalline silicon oxide film formed in the oxidation step. Consists of.
以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.
第１図（ａ）〜（ｃ）は本発明をＣＣＤ素子の製造に実
施した場合の一実施例を示す部分工程図で、第１のゲー
ト酸化膜の形成から第２層目の多結晶シリコン層のパタ
ーン形成までを示したものである。まず、第１図（ａ）
に示すように、半導体基板１の一つの主面の所定域にゲ
ート酸化膜および容量を構成する薄いシリコン酸化膜２
を形成し、この上にリンを拡散した第１層目の多結晶シ
リコン層３をパターン形成する。次に第１図（ｂ）に示
すように、この多結晶シリコン層３をマスクにしてシリ
コン酸化膜２をある程度の厚さを残してエツチング除去
する。ついで、第１図（ｃ）に示すように、第２のゲー
ト酸化膜となるシリコン酸化膜４を形成し再びリンを拡
散した第２層目の多結晶シリコン層５のパターンを形成
する。本発明によれば、上記実施例が示すように、シリ
コン酸化膜２が一部の厚さを残してエツチングされるの
で、第１層目の多結晶シリコン層３が熱酸化される際、
多結晶シリコン層３内に含まれるリン（Ｐ）の基板内へ
の拡散は防止される。FIGS. 1(a) to 1(c) are partial process diagrams showing an embodiment of the present invention in the manufacture of a CCD element, from the formation of a first gate oxide film to the formation of a second layer of polycrystalline silicon. This figure shows the steps up to layer pattern formation. First, Figure 1(a)
As shown in FIG. 2, a thin silicon oxide film 2 constituting a gate oxide film and a capacitor is formed in a predetermined area on one main surface of a semiconductor substrate 1.
is formed, and a first polycrystalline silicon layer 3 in which phosphorus is diffused is patterned thereon. Next, as shown in FIG. 1(b), using this polycrystalline silicon layer 3 as a mask, the silicon oxide film 2 is etched away leaving a certain thickness. Next, as shown in FIG. 1(c), a silicon oxide film 4 which will become a second gate oxide film is formed, and a pattern of a second polycrystalline silicon layer 5 in which phosphorus is diffused is again formed. According to the present invention, as shown in the above embodiment, the silicon oxide film 2 is etched leaving a part of the thickness, so when the first polycrystalline silicon layer 3 is thermally oxidized,
Phosphorus (P) contained in polycrystalline silicon layer 3 is prevented from diffusing into the substrate.
第２図（ａ）〜（Ｃ）は本発明をＤ−ＲＡＭ素子の製造
に実施した場合の一実施例を示す工程図である。本実施
例においても、第２図（ｂ）が示すように、第１のゲー
ト酸化膜となるシリコン酸化８２は、第１層目の多結晶
シリコン層３をマスクにしである程度の厚さを残してエ
ツチング除去される。従って、この残されたシリコン酸
化膜によって、リン（Ｐ）の基板内への外向拡散を防ぐ
ことができる。ここで、６はフィールド酸化膜を示す。FIGS. 2(a) to 2(C) are process diagrams showing one embodiment of the present invention in the manufacture of a D-RAM element. In this embodiment as well, as shown in FIG. 2(b), the silicon oxide 82 which becomes the first gate oxide film is formed using the first polycrystalline silicon layer 3 as a mask, leaving a certain thickness. It is removed by etching. Therefore, this remaining silicon oxide film can prevent outward diffusion of phosphorus (P) into the substrate. Here, 6 indicates a field oxide film.
以上説明したように、本発明によれば、第１層目のシリ
コン酸化膜を第１層目の多結晶シリコン層をマスクにし
て、ある程度の厚さを残してエツチングするので、この
あと多結晶シリコン層の表面を酸化する熱酸化工程を行
ったとしても、第１層目の多結晶シリコン層からのリン
（Ｐ）の外向拡散を防ぐことが可能である。従って、デ
バイスの特性異常を防ぐことができ、生産歩留りを著し
く向上せしめ得る効果を有する。As explained above, according to the present invention, the first layer of silicon oxide film is etched using the first layer of polycrystalline silicon layer as a mask, leaving a certain thickness. Even if a thermal oxidation step is performed to oxidize the surface of the silicon layer, outward diffusion of phosphorus (P) from the first polycrystalline silicon layer can be prevented. Therefore, abnormal characteristics of the device can be prevented and production yield can be significantly improved.
第１図（ａ）〜（ｃ）は本発明をＣＣＤ素子の製造に実
施した場合の一実施例を示す部分工程図、第２図（ａ）
〜（ｃ）は本発明をＤ−ＲＡＭ素子の製造に実施した場
合の一実施例を示す工程図、第３図（ａ）〜（ｃ）はリ
ン（Ｐ）を含む２層の多結晶シリコンケート電極を有す
る半導体装置の従来の製造方法を示す工程図である。
１・・・半導体基板、２．４・・・シリコン酸化膜、３
・・・第１層目の多結晶シリコン層、５・・・第２層目
の多結晶シリコン層、６・・・フィールド酸化膜。
代理人 弁理士 内 原 音
（α）
（ｂ）
（Ｃン
第ｆ閃
（α）
（ｂ）
第２図
３．５５糸も晶゛ノ′ｊ］゛ノ
（α）
（ｂ）
（ＣＩ
第３図FIGS. 1(a) to (c) are partial process diagrams showing one embodiment of the present invention in the manufacture of a CCD element, and FIG. 2(a)
~(c) is a process diagram showing an example of the production of a D-RAM element according to the present invention, and Figures 3(a) to (c) are two-layer polycrystalline silicon containing phosphorus (P). 1 is a process diagram showing a conventional manufacturing method of a semiconductor device having a gate electrode. 1... Semiconductor substrate, 2.4... Silicon oxide film, 3
. . . first layer polycrystalline silicon layer, 5 . . . second layer polycrystalline silicon layer, 6 . . . field oxide film. Agent Patent Attorney Oto Uchihara (α) (b) (Cf flash (α) (b) Figure 3
Claims (1)
成する工程と、前記ゲート酸化膜上にリンを含む第１層
目の多結晶シリコン層をパターン形成する工程と、前記
第１層目の多結晶シリコン層に覆われることなく露呈す
る前記ゲート酸化膜をある程度の厚さを残してエッチン
グ除去する工程と、前記第１層目の多結晶シリコン層の
表面を再度酸化する工程と、前記酸化工程で形成される
多結晶シリコン酸化膜上に一部を延在させて第２層目の
多結晶シリコン層を形成する工程とを含むことを特徴と
する半導体装置の製造方法。forming a gate oxide film in a predetermined area on a semiconductor substrate of one conductivity type; patterning a first polycrystalline silicon layer containing phosphorus on the gate oxide film; a step of etching away the exposed gate oxide film without being covered by the polycrystalline silicon layer of the first layer, and a step of oxidizing the surface of the first polycrystalline silicon layer again; 1. A method for manufacturing a semiconductor device, comprising the step of forming a second polycrystalline silicon layer by partially extending over the polycrystalline silicon oxide film formed in the oxidation step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63110988A JPH0736420B2 (en) | 1988-05-06 | 1988-05-06 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63110988A JPH0736420B2 (en) | 1988-05-06 | 1988-05-06 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01280336A true JPH01280336A (en) | 1989-11-10 |
| JPH0736420B2 JPH0736420B2 (en) | 1995-04-19 |
Family
ID=14549557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63110988A Expired - Lifetime JPH0736420B2 (en) | 1988-05-06 | 1988-05-06 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0736420B2 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55115366A (en) * | 1979-02-26 | 1980-09-05 | Matsushita Electric Ind Co Ltd | Manufacturing method of charge transfer unit |
| JPS59132634A (en) * | 1983-01-19 | 1984-07-30 | Sanyo Electric Co Ltd | Method of multilayer interconnection |
| JPS6158257A (en) * | 1984-08-29 | 1986-03-25 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6292373A (en) * | 1985-10-17 | 1987-04-27 | Ricoh Co Ltd | Manufacture of semiconductor device in which autodoping is prevented |
-
1988
- 1988-05-06 JP JP63110988A patent/JPH0736420B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55115366A (en) * | 1979-02-26 | 1980-09-05 | Matsushita Electric Ind Co Ltd | Manufacturing method of charge transfer unit |
| JPS59132634A (en) * | 1983-01-19 | 1984-07-30 | Sanyo Electric Co Ltd | Method of multilayer interconnection |
| JPS6158257A (en) * | 1984-08-29 | 1986-03-25 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6292373A (en) * | 1985-10-17 | 1987-04-27 | Ricoh Co Ltd | Manufacture of semiconductor device in which autodoping is prevented |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0736420B2 (en) | 1995-04-19 |
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