JPS6310572A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6310572A JPS6310572A JP15550986A JP15550986A JPS6310572A JP S6310572 A JPS6310572 A JP S6310572A JP 15550986 A JP15550986 A JP 15550986A JP 15550986 A JP15550986 A JP 15550986A JP S6310572 A JPS6310572 A JP S6310572A
- Authority
- JP
- Japan
- Prior art keywords
- film
- pattern
- metal silicide
- polycrystalline silicon
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 29
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000012212 insulator Substances 0.000 claims abstract description 8
- 238000001947 vapour-phase growth Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 11
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 abstract description 4
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910008479 TiSi2 Inorganic materials 0.000 abstract description 2
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 229910008814 WSi2 Inorganic materials 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法、特に、電極配線部など
に多結晶シリコン膜と金属シリサイド膜の二層膜が用い
られる半導体装置の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, particularly a method for manufacturing a semiconductor device in which a two-layer film of a polycrystalline silicon film and a metal silicide film is used in an electrode wiring portion, etc. Regarding.
従来、ＭＯＳトランジスタのゲート電極を作る場合、金
属シリサイド膜と多結晶シリコン膜の二層膜を用い、１
度のフォトプロセスによって金属シリサイド膜及び多結
晶シリコン膜をそれぞれ食刻し、パターンを形成してい
た。Conventionally, when making the gate electrode of a MOS transistor, a two-layer film of a metal silicide film and a polycrystalline silicon film is used.
The metal silicide film and the polycrystalline silicon film were each etched using a photo process to form a pattern.
上述した従来の製造方法は、フォトプロセス法の７オト
レジストをマスクとして金属シリサイド膜及び多結晶シ
リコン膜を食刻している。この為、エツチング条件がフ
ォトレジストの耐エツチング特性が悪い為に７オトレジ
スト膜と金属シリサイド膜及び多結晶シリコン膜との選
択比により限定されること、及び、フォトレジスト膜パ
ターンが食刻時間により変化し、細化する欠点がある。In the conventional manufacturing method described above, the metal silicide film and the polycrystalline silicon film are etched using a photo resist as a mask. For this reason, the etching conditions are limited by the selectivity of the photoresist film, metal silicide film, and polycrystalline silicon film due to the poor etching resistance of the photoresist, and the photoresist film pattern changes depending on the etching time. However, it has the disadvantage of becoming thinner.
また、エツチング条件が上記により限定されている為、
エツチング形状の改善が難かしく、金属シリサイドパタ
ーンに比べて多結晶シリコン膜パターンが小さくなりや
すい欠点を有している。In addition, since the etching conditions are limited as above,
It is difficult to improve the etching shape, and the polycrystalline silicon film pattern tends to be smaller than a metal silicide pattern.
本発明の製造方法は、金属シリサイド膜の上に気相成長
法によりシリコン酸化膜、シリコン窒化膜などの絶縁体
膜を形成し、そ扛から、フォトプロセス法を用いて前記
絶縁体膜のパターン形成を行なう、つぎに、この絶縁体
膜パターンをマスクとして前記の金属シリサイド膜及び
多結晶シリコン模を順次文刻し、パターン形成を行なう
ことを含んでいる。In the manufacturing method of the present invention, an insulating film such as a silicon oxide film or a silicon nitride film is formed on a metal silicide film by a vapor phase growth method, and then a pattern of the insulating film is formed using a photo process method. Next, using this insulating film pattern as a mask, the metal silicide film and the polycrystalline silicon pattern are sequentially engraved to form a pattern.
この方法を用いると、絶縁体膜はフォトレジストに比べ
て耐エツチング性に優れている為、エツチング条件の選
択性が増し、その結果、所望のエツチング形状を得るこ
とが可能となる。又、金属シリサイド膜上に気相成長法
による絶縁体膜を形成している為、金属シリサイドパタ
ーン形成後に、多結晶シリコン膜側壁に、熱酸化により
シリコン酸化膜を形成する時に、絶縁体膜が酸化剤の酸
素の拡散のマスクとなり、酸素により金属シリサイドと
多結晶シリコン界面にシリコン酸化膜が形成されること
を防止できる。この結果、金属シリサイド膜のノ・ガレ
不良を大幅に低減できる長所がある。When this method is used, since the insulating film has better etching resistance than photoresist, the selectivity of etching conditions increases, and as a result, it becomes possible to obtain a desired etched shape. In addition, since the insulating film is formed on the metal silicide film by vapor phase growth, when a silicon oxide film is formed by thermal oxidation on the sidewall of the polycrystalline silicon film after forming the metal silicide pattern, the insulating film is It serves as a mask for the diffusion of oxygen, an oxidizing agent, and can prevent the formation of a silicon oxide film at the interface between metal silicide and polycrystalline silicon due to oxygen. As a result, there is an advantage that defects such as cracks and cracks in the metal silicide film can be significantly reduced.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）ないしくｄ）は本発明の一実施例に係るＭ
ＯＳトランジスタのゲート電極の形成工程について説明
するだめの断面図である。まず第１図ｔａｌの：うに、
半導体基板１上にシリコン酸化膜２、不純物を添加した
多結晶シリコン膜３、ＴｉＳｉ２ 。FIGS. 1(a) to d) show M according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a process of forming a gate electrode of an OS transistor. First of all, in Figure 1 tal: sea urchin,
A silicon oxide film 2, an impurity-doped polycrystalline silicon film 3, and a TiSi2 film are formed on a semiconductor substrate 1.
Ｗ８ｉ、などの金属シリサイド膜４、および、気相成長
法によるシリコン酸化膜５の４層膜を形成し、その上に
、フォトプロセス法により、フォトレジストパターン６
を形成する。それぞれの膜厚は、に、フォトレジスト６
をマスクとして、シリコン酸化膜５を食刻し、シリコン
酸化膜パターン５ａを形成する。つぎに同図（Ｃ１のよ
うに、シリコン酸化膜パターン５ａをマスクとして、金
属シリサイド膜４をエツチングし、金属シリサイドパタ
ーン４ａを形成する。この時のエツチング方法は、アル
カリ系薬品を用いた湿式エツチング法でも、ＣＦ４系ガ
スを用いたプラズマエツチング法でも良く、必要に応じ
て選択することができる。次に同図（ｄ）のように、シ
リコン酸化膜パターン４ａを用いて、多結晶シリコン膜
３を、ＣＣｌ４系ガスを用いた、異方性プラズマエツチ
ング法によりエツチングし、多結晶シリコン膜パターン
３ａを形成する。それカラ、ソース、ドレイン拡散、ソ
ース、ドレインの電極形成などを経てＭＯＳ）ランジス
タを完成する。A four-layer film of a metal silicide film 4 such as W8i and a silicon oxide film 5 is formed by vapor phase growth, and a photoresist pattern 6 is formed thereon by a photo process method.
form. The film thickness of each photoresist is 6.
Using as a mask, the silicon oxide film 5 is etched to form a silicon oxide film pattern 5a. Next, as shown in the same figure (C1), the metal silicide film 4 is etched using the silicon oxide film pattern 5a as a mask to form a metal silicide pattern 4a.The etching method used at this time is wet etching using an alkaline chemical. or a plasma etching method using CF4 gas, which can be selected as required.Next, as shown in FIG. is etched by an anisotropic plasma etching method using a CCl4-based gas to form a polycrystalline silicon film pattern 3a.After performing color, source, and drain diffusion, and formation of source and drain electrodes, a MOS transistor is formed. Complete.
以上、説明したように本発明は、金属シリサイド膜上に
、気相成長法による絶縁体膜を形成する。As described above, in the present invention, an insulator film is formed on a metal silicide film by vapor phase growth.
この絶縁体膜を金属シリサイド膜及び多結晶シリコン膜
のパターン形成時のマスクとして使用することにより、
従来のフォトプロセス法のフォトレジストのマスクに比
べてエツチング条件の選択性が大幅に増加し、金属シリ
サイド膜及び多結晶シリコン膜のエツチング形状を任意
に調整できる効果がある。又、この絶縁体膜を多結晶シ
リコン漠の側壁を熱酸化するときの酸化剤の拡散のマス
クとして用いると、酸化時に、金属シリサイド膜と多結
晶シリコン膜界面にシリコン酸化膜が形成されるのを防
止でき、その結果、金属シリサイド膜のハガレ不良を大
幅に低減できる効果がある。By using this insulator film as a mask during patterning of metal silicide films and polycrystalline silicon films,
The selectivity of etching conditions is greatly increased compared to the photoresist mask used in conventional photoprocessing methods, and the etching shape of the metal silicide film and polycrystalline silicon film can be adjusted arbitrarily. Furthermore, if this insulator film is used as a mask for the diffusion of the oxidant when thermally oxidizing the sidewalls of the polycrystalline silicon film, a silicon oxide film will be formed at the interface between the metal silicide film and the polycrystalline silicon film during oxidation. As a result, peeling defects of the metal silicide film can be significantly reduced.
第１図（ａ）〜（ｄ）は、本発明の一実施例に係るＭＯ
Ｓトランジスタのゲート電極形成法を説明するための工
程順の断面図である。
１・・−・・・シリコン基板、２・・・・・・シリコン
酸化膜、３・・・・・・多結晶シリコン膜、３ａ・・・
・・・多結晶シリコン膜パターン、４・・・・・・金属
シリサイド膜、４ａ・・・・・・金属シリサイド膜パタ
ーン、５・・・・・・気相成長シリコン酸化膜、５；ｌ
・・・・・・気相成長酸化膜パターン、６・・・・・・
フォトレジストパターン。
代理人 弁理士 内 原 日１
−茶 ｆＴＩＪFIGS. 1(a) to 1(d) show an MO according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the order of steps for explaining a method for forming a gate electrode of an S transistor. 1...Silicon substrate, 2...Silicon oxide film, 3...Polycrystalline silicon film, 3a...
...Polycrystalline silicon film pattern, 4...Metal silicide film, 4a...Metal silicide film pattern, 5...Vapor-phase growth silicon oxide film, 5;l
・・・・・・Vapor-phase growth oxide film pattern, 6・・・・・・
photoresist pattern. Agent Patent Attorney Uchihara Hi 1 - Tea fTIJ
Claims (1)
金属シリサイド膜及び気相成長法による絶縁体膜を順次
形成する工程と、フォトプロセス法を用いて該絶縁体膜
を部分的に食刻する工程と、残存する絶縁体膜をマスク
として前記金属シリサイド膜、及び多結晶シリコン膜を
順次エッチングする工程とを含むことを特徴とする半導
体装置の製造方法。Silicon oxide film, polycrystalline silicon film,
A step of sequentially forming a metal silicide film and an insulator film by vapor phase growth, a step of partially etching the insulator film using a photo process method, and a step of etching the metal silicide film using the remaining insulator film as a mask. 1. A method for manufacturing a semiconductor device, comprising the steps of sequentially etching a polycrystalline silicon film and a polycrystalline silicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15550986A JPS6310572A (en) | 1986-07-01 | 1986-07-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15550986A JPS6310572A (en) | 1986-07-01 | 1986-07-01 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6310572A true JPS6310572A (en) | 1988-01-18 |
Family
ID=15607604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15550986A Pending JPS6310572A (en) | 1986-07-01 | 1986-07-01 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6310572A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19516339B4 (en) * | 1994-06-08 | 2006-03-16 | Samsung Electronics Co., Ltd., Suwon | Method for producing a semiconductor component with a low-resistance gate electrode |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49115659A (en) * | 1973-03-07 | 1974-11-05 | ||
| JPS55120170A (en) * | 1979-03-12 | 1980-09-16 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Mos type semiconductor device |
-
1986
- 1986-07-01 JP JP15550986A patent/JPS6310572A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49115659A (en) * | 1973-03-07 | 1974-11-05 | ||
| JPS55120170A (en) * | 1979-03-12 | 1980-09-16 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Mos type semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19516339B4 (en) * | 1994-06-08 | 2006-03-16 | Samsung Electronics Co., Ltd., Suwon | Method for producing a semiconductor component with a low-resistance gate electrode |
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