KR20010039009A - Method of fabricating gate - Google Patents
Method of fabricating gate Download PDFInfo
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- KR20010039009A KR20010039009A KR1019990047214A KR19990047214A KR20010039009A KR 20010039009 A KR20010039009 A KR 20010039009A KR 1019990047214 A KR1019990047214 A KR 1019990047214A KR 19990047214 A KR19990047214 A KR 19990047214A KR 20010039009 A KR20010039009 A KR 20010039009A
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- tungsten
- oxide film
- gate electrode
- gate
- layer
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- 238000004519 manufacturing process Methods 0.000 title description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 42
- 239000010937 tungsten Substances 0.000 claims abstract description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000001257 hydrogen Substances 0.000 claims abstract description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 abstract 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 15
- 229910001930 tungsten oxide Inorganic materials 0.000 description 15
- 238000010405 reoxidation reaction Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 게이트전극 형성방법에 관한 것으로, 특히, 텅스텐/다결정실리콘의 2중 적층된 구조를 갖는 게이트전극 패터닝 시, 게이트전극 저항을 증가시키지 않고도 선택적 재산화 공정을 용이하게 진행시킬 수 있는 게이트전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate electrode, and more particularly, in a gate electrode patterning having a double stacked structure of tungsten / polycrystalline silicon, a gate electrode capable of easily performing a selective reoxidation process without increasing the gate electrode resistance. It relates to a formation method.
게이트전극으로 텅스텐/다결정실리콘의 2중 적층 구조를 갖는 반도체 소자 제조에서는 텅스텐층/다결정실리콘층을 패턴 식각할 시에 게이트산화막이 손상되므로, 게이트전극 저항은 그대로 유지하면서 손상된 게이트산화막을 회복하기 위해 텅스텐막은 산화시키지 않고 실리콘만 산화시키는 과정이 선택적 재산화 과정이 수반된다.In the fabrication of a semiconductor device having a double stacked structure of tungsten / polycrystalline silicon as the gate electrode, the gate oxide film is damaged when the tungsten layer / polycrystalline silicon layer is pattern-etched, so as to recover the damaged gate oxide film while maintaining the gate electrode resistance. The process of oxidizing only silicon without oxidizing a tungsten film involves selective reoxidation.
도 1a 내지 도 1b는 종래기술에 따른 게이트전극 형성과정을 보인 공정단면도이다.1A through 1B are cross-sectional views illustrating a process of forming a gate electrode according to the related art.
도 2는 재산화 공정 시, 텅스텐은 산화되지 않으면서 실리콘막만 산화되는 이론치 온도범위를 도시한 그래프이다.2 is a graph showing a theoretical temperature range in which only a silicon film is oxidized without tungsten being oxidized during the reoxidation process.
도 1a와 같이, 반도체기판(100) 상에 도면에 도시되지는 않았지만, 웰(well) 및 필드산화막(field oxide) 등을 형성한다.As shown in FIG. 1A, a well, a field oxide film, and the like are formed on the semiconductor substrate 100, although not shown in the drawing.
이 후, 반도체기판(100) 상에 산화실리콘 등을 화학기상증착(Chemical Vapor Deposition: 이하, CVD라 칭함)하여 게이트산화막(102)을 형성한다.Thereafter, silicon oxide or the like is deposited on the semiconductor substrate 100 to form a gate oxide film 102 by chemical vapor deposition (hereinafter, referred to as CVD).
그리고 게이트산화막(102) 상에 다결정실리콘층 및 텅스텐층을 순차적으로 형성한다.Then, a polysilicon layer and a tungsten layer are sequentially formed on the gate oxide film 102.
이 후, 다결정실리콘층 및 텅스텐층을 패턴 식각하여 게이트전극(110)을 형성한다.Thereafter, the polysilicon layer and the tungsten layer are pattern-etched to form the gate electrode 110.
이 게이트전극(110)은 도면에서와 같이, 텅스텐/다결정실리콘 패턴(106)/(104)의 이중 구조를 갖는다.This gate electrode 110 has a double structure of tungsten / polycrystalline silicon patterns 106/104 as shown in the figure.
상기의 다결정실리콘층/텅스텐층 패턴 식각 시에는 게이트산화막(102)이 손상된다.When the polysilicon layer / tungsten layer pattern is etched, the gate oxide layer 102 is damaged.
따라서, 게이트전극(110) 형성 후에는 도 1b와 같이, 선택적 재산화 공정을 거쳐 게이트전극 저항을 그대로 유지하면서 손상된 게이트산화막을 회복시킨다.Therefore, after the gate electrode 110 is formed, the damaged gate oxide film is recovered while maintaining the gate electrode resistance as it is through the selective reoxidation process as shown in FIG. 1B.
즉, 선택적 재산화 공정은 반도체기판(100) 상의 노출된 실리콘막인 게이트산화막(102) 표면 및 폴리실리콘패턴(104) 측면만을 산화시키고, 텅스텐패턴(106)은 산화되지 않도록 해야 한다.That is, the selective reoxidation process should oxidize only the surface of the gate oxide film 102 and the polysilicon pattern 104 side, which are exposed silicon films on the semiconductor substrate 100, and prevent the tungsten pattern 106 from being oxidized.
재산화 과정에서, 게이트산화막(102) 표면에는 제 1산화막(108)이 형성되고, 또한, 폴리실리콘패턴(104)에는 노출된 측면으로 산화됨에 따라 제 2산화막(120)이 형성된다.In the reoxidation process, the first oxide film 108 is formed on the surface of the gate oxide film 102, and the second oxide film 120 is formed on the polysilicon pattern 104 as it is oxidized to the exposed side surface.
도면에서와 같이, 폴리실리콘패턴(104)은 노출된 측면으로 산화되어 텅스텐패턴(106)보다도 패턴크기가 작아지게 된다.As shown in the figure, the polysilicon pattern 104 is oxidized to the exposed side, so that the pattern size is smaller than that of the tungsten pattern 106.
즉, 재산화 과정에서, 실리콘막은 산화되어 SiO2막인 제 1, 제 2산화막(108)(120)이 되며, 텅스텐패턴(106)도 WO3막인 텅스텐산화막이 형성되나, 도 2와 같이, 빗금친 영역 내에서는 텅스텐산화막이 환원되고, 실리콘 성분은 산화된다.That is, in the reoxidation process, the silicon film is oxidized to become the first and second oxide films 108 and 120 which are SiO 2 films, and the tungsten oxide film which is also the WO 3 film is formed as the tungsten pattern 106, but as shown in FIG. In the parent region, the tungsten oxide film is reduced and the silicon component is oxidized.
Si ⇒ SiO2(산화)Si ⇒ SiO 2 (oxidation)
WO3⇒W (환원)WO 3 ⇒ W (reduction)
그러나, 이론적으로는 빗금친 영역 내에서는 텅스텐은 산화되지 않고 실리콘막만이 산화되어야 하지만, 실제로는 텅스텐 표면에도 소정두께의 텅스텐산화막(WO3)이 형성된다.In theory, however, tungsten is not oxidized in the hatched region and only the silicon film should be oxidized, but in reality, a tungsten oxide film WO 3 having a predetermined thickness is also formed on the tungsten surface.
따라서, 종래의 기술에서는 텅스텐 표면에 텅스텐산화막이 형성됨에 따라, 게이트전극의 저항이 증가하는 문제점이 발생되었다.Therefore, in the related art, as the tungsten oxide film is formed on the tungsten surface, a problem of increasing the resistance of the gate electrode has occurred.
상기의 문제점을 해결하고자, 본 발명의 목적은 폴리실리콘/텅스텐의 이중 구조를 갖는 게이트전극에서, 텅스텐 표면에 산화막이 발생되는 것을 방지할 수 있는 게이트전극 형성방법에 있다.In order to solve the above problems, an object of the present invention is to form a gate electrode that can prevent the oxide film is generated on the surface of the tungsten in the gate electrode having a double structure of polysilicon / tungsten.
상기 목적을 달성하고자, 본 발명의 게이트전극 형성방법은 반도체기판 상에 게이트산화막을 형성하는 공정과, 게이트산화막 상에 텅스텐층 및 다결정실리콘층을 순차적으로 적층하는 공정과, 텅스텐층과 다결정실리콘층을 패턴 식각하여 2중 구조를 갖는 게이트전극을 형성하는 공정과, 게이트산화막 및 잔류된 다결정실리콘층을 산화시키는 공정과, 수소분위기에서 잔류된 상기 텅스텐층을 열처리시키는 공정을 구비한 것이 특징이다.In order to achieve the above object, the gate electrode forming method of the present invention comprises the steps of forming a gate oxide film on a semiconductor substrate, sequentially stacking a tungsten layer and a polysilicon layer on the gate oxide film, a tungsten layer and a polycrystalline silicon layer Pattern etching to form a gate electrode having a double structure, oxidizing the gate oxide film and the remaining polysilicon layer, and heat-treating the tungsten layer remaining in a hydrogen atmosphere.
도 1a 내지 도 1b는 종래기술에 따른 게이트전극 형성과정을 보인 공정단면도이고,1A through 1B are cross-sectional views illustrating a process of forming a gate electrode according to the related art.
도 2는 재산화 공정 시, 텅스텐은 산화되지 않으면서 실리콘막만 산화되는 이론치 온도범위를 도시한 그래프이다.2 is a graph showing a theoretical temperature range in which only a silicon film is oxidized without tungsten being oxidized during the reoxidation process.
도 3a 내지 도 3c는 본 발명에 따른 게이트전극 형성과정을 보인 공정단면도이고,3A to 3C are cross-sectional views illustrating a process of forming a gate electrode according to the present invention;
도 4는 본 발명에 따른 텅스텐산화막이 텅스텐으로 환원되는 온도범위를 도시한 그래프이다.4 is a graph showing a temperature range in which a tungsten oxide film is reduced to tungsten according to the present invention.
*도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100, 200. 반도체기판 102, 202. 게이트산화막100, 200. Semiconductor substrate 102, 202. Gate oxide film
104, 204. 다결정실리콘패턴 106, 206. 텅스텐패턴104, 204. Polycrystalline silicon pattern 106, 206. Tungsten pattern
110, 210. 게이트전극 222. 텅스텐산화막110, 210. Gate electrode 222. Tungsten oxide film
108, 120, 208, 220. 산화막 230. 열처리108, 120, 208, 220. Oxide film 230. Heat treatment
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하겠다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 3a 내지 도 3c는 본 발명에 따른 게이트전극 형성과정을 보인 공정단면도이고, 도 4는 본 발명에 따른 텅스텐산화막이 텅스텐으로 환원되는 온도범위를 도시한 그래프이다.3A to 3C are cross-sectional views illustrating a process of forming a gate electrode according to the present invention, and FIG. 4 is a graph showing a temperature range in which a tungsten oxide film is reduced to tungsten according to the present invention.
도 3a와 같이, 반도체기판(200) 상에 통상적인 반도체 제조 공정에서와 같이, 웰 및 필드산화막 등이 형성된다.(미도시)As shown in FIG. 3A, a well, a field oxide film, and the like are formed on the semiconductor substrate 200 as in a conventional semiconductor manufacturing process.
상기 구조를 갖는 반도체기판(200)에 산화실리콘 등을 CVD하여 게이트산화막(202)을 형성한다.A silicon oxide or the like is CVD on the semiconductor substrate 200 having the above structure to form a gate oxide film 202.
그리고 게이트산화막(202) 상에 게이트전극 형성을 위한 재료인 다결정실리콘층(미도시) 및 텅스텐층(미도시)을 순차적으로 적층한다.A polysilicon layer (not shown) and a tungsten layer (not shown), which are materials for forming a gate electrode, are sequentially stacked on the gate oxide film 202.
이 후, 텅스텐층 상에 게이트전극 형성영역이 정의된 감광막패턴(미도시)을 형성한 후, 이 감광막패턴을 마스크로 하여 텅스텐층 및 다결정실리콘층을 식각함으로써 2중 구조를 갖는 게이트전극(210)을 형성한다. 게이트전극(210)은 도면에서와 같이, 텅스텐/다결정실리콘패턴(206)(204)으로 이루어진다. 그리고 감광막패턴은 제거된다.Thereafter, a photoresist pattern (not shown) in which a gate electrode formation region is defined is formed on the tungsten layer, and then the tungsten layer and the polysilicon layer are etched using the photoresist pattern as a mask to form a gate electrode 210 having a double structure. ). The gate electrode 210 is made of tungsten / polycrystalline silicon patterns 206 and 204 as shown in the figure. And the photoresist pattern is removed.
이 후에는, 식각 과정에서 게이트산화막(202)은 쉽게 손상되므로, 손상된 게이트산화막을 회복시키기 위한 재산화 공정이 필요하다.Afterwards, the gate oxide film 202 is easily damaged during the etching process, so that a reoxidation process is required to recover the damaged gate oxide film.
도 3b와 같이, 재산화 공정에서는 산소 또는 H2O 분위기에서 게이트산화막(202) 표면 및 다결정실리콘패턴(204) 측면을 노출시킨다.As shown in FIG. 3B, the reoxidation process exposes the gate oxide film 202 surface and the polysilicon pattern 204 side surface in an oxygen or H 2 O atmosphere.
이 결과, 게이트산화막(202) 표면에는 제 1산화막(208)이 형성되고, 다결정실리콘 패턴(204) 측면에는 제 2산화막(220)이 형성된다.As a result, the first oxide film 208 is formed on the surface of the gate oxide film 202, and the second oxide film 220 is formed on the side surface of the polysilicon pattern 204.
또한, 텅스텐패턴(206)에도 소정두께의 텅스텐산화막(222)이 형성되나, 이 텅스텐산화막(222)은 게이트전극 저항을 증가시키므로, 본 발명에서는 텅스텐산화막을 제거하는 공정이 별도로 수반된다.In addition, a tungsten oxide film 222 having a predetermined thickness is also formed on the tungsten pattern 206. Since the tungsten oxide film 222 increases the gate electrode resistance, the present invention involves a process of removing the tungsten oxide film separately.
도 3c와 같이, 수소분위기에서 열처리(230)하여 텅스텐산화막을 제거한다.As shown in FIG. 3C, the tungsten oxide film is removed by heat treatment 230 in a hydrogen atmosphere.
도 4는 수소분위기에서 텅스텐산화막(WO3)이 텅스텐으로 환원되는 범위를 나타내준다.4 shows a range in which the tungsten oxide film WO 3 is reduced to tungsten in a hydrogen atmosphere.
즉, 도 4에서 알 수 있듯이, 1500℃ 까지 제 1, 제 2산화막(208)(220)은 안정하지만, 텅스텐산화막은 800℃ 이상에서는 텅스텐으로 환원된다.That is, as can be seen in FIG. 4, the first and second oxide films 208 and 220 are stable up to 1500 ° C., but the tungsten oxide film is reduced to tungsten at 800 ° C. or higher.
상술한 바와 같이, 본 발명에서는 텅스텐/다결정실리콘의 이중 구조를 갖는 게이트전극을 형성할 시, 손상된 게이트산화막을 회복시키기 위한 재산화 공정을 진행시키는 동안 형성된 텅스텐산화막을 제거하는 공정이 수반된다.As described above, in the present invention, when forming a gate electrode having a double structure of tungsten / polycrystalline silicon, a process of removing the tungsten oxide film formed during the reoxidation process for recovering the damaged gate oxide film is involved.
즉, 본 발명에서는 텅스텐산화막을 텅스텐으로 환원시키는 공정이 수반됨에 따라, 게이트전극 저항의 증가를 방지할 수 있다.That is, according to the present invention, as the process of reducing the tungsten oxide film to tungsten is involved, an increase in the gate electrode resistance can be prevented.
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| KR10-1999-0047214A KR100525119B1 (en) | 1999-10-28 | 1999-10-28 | Method of fabricating gate |
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| KR10-1999-0047214A KR100525119B1 (en) | 1999-10-28 | 1999-10-28 | Method of fabricating gate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7371669B2 (en) | 2004-11-19 | 2008-05-13 | Samsung Electronics Co., Ltd. | Method of forming a gate of a semiconductor device |
| CN107437500A (en) * | 2016-05-26 | 2017-12-05 | 北大方正集团有限公司 | The manufacture method and polysilicon gate of a kind of polysilicon gate |
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1999
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7371669B2 (en) | 2004-11-19 | 2008-05-13 | Samsung Electronics Co., Ltd. | Method of forming a gate of a semiconductor device |
| CN107437500A (en) * | 2016-05-26 | 2017-12-05 | 北大方正集团有限公司 | The manufacture method and polysilicon gate of a kind of polysilicon gate |
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| KR100525119B1 (en) | 2005-11-01 |
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