KR100411393B1 - Method for forming the gate electrode pattern in semiconductor device - Google Patents
Method for forming the gate electrode pattern in semiconductor device Download PDFInfo
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- KR100411393B1 KR100411393B1 KR10-2001-0033877A KR20010033877A KR100411393B1 KR 100411393 B1 KR100411393 B1 KR 100411393B1 KR 20010033877 A KR20010033877 A KR 20010033877A KR 100411393 B1 KR100411393 B1 KR 100411393B1
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- polysilicon
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 75
- 229920005591 polysilicon Polymers 0.000 claims abstract description 75
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims description 4
- 230000007261 regionalization Effects 0.000 claims 1
- 239000010936 titanium Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체소자의 게이트전극 패턴 형성방법에 관한 것으로, 특히 반도체기판 상에 게이트산화막, 폴리실리콘층, 금속막 및 마스크산화막을 순차적으로 적층한 후, 식각 공정을 진행하여 게이트전극을 패터닝하여 게이트전극 패턴을 형성함에 있어서, 상기 폴리실리콘층 증착 시, 도프트 폴리실리콘층, 언도프트 폴리실리콘층 및 도프트 폴리실리콘층을 순차적으로 증착하여 다층구조의 폴리실리콘 패턴을 형성하는 것을 특징으로 하여, 후속 게이트 라이트 산화 공정 시, 폴리실리콘막이 산화되어 블로우업(blow-up)현상이 발생하는 것을 억제하여 게이트전극 패턴의 프로파일이 개선되며, 그에 따른 반도체소자의 특성, 신뢰성 및 수율을 향상시키는 기술로 매우 유용하고 효과적인 장점을 지닌 발명에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode pattern of a semiconductor device. In particular, a gate oxide film, a polysilicon layer, a metal film, and a mask oxide film are sequentially stacked on a semiconductor substrate, and then the gate electrode is patterned by etching. In forming an electrode pattern, when the polysilicon layer is deposited, a doped polysilicon layer, an undoped polysilicon layer, and a doped polysilicon layer are sequentially deposited to form a polysilicon pattern having a multilayer structure. In the subsequent gate light oxidation process, the polysilicon film is oxidized to suppress blow-up, thereby improving the profile of the gate electrode pattern, thereby improving the characteristics, reliability, and yield of the semiconductor device. The invention relates to an invention with very useful and effective advantages.
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 보다 상세하게는, 게이트전극 패턴 중 폴리실리콘층 증착 시, 도프트 폴리실리콘층, 언도프트 폴리실리콘층 및 도프트 폴리실리콘층을 순차적으로 증착하여 다층구조의 폴리실리콘 패턴을 형성함으로써, 후속 게이트 라이트 산화 공정 시, 폴리실리콘층의 중간부분이 산화되어 블로우업(blow-up)현상이 발생하는 것을 억제하여 게이트전극 패턴의 프로파일을 개선할 수 있도록 하는 반도체소자의 게이트전극 패턴 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to deposit a polysilicon layer in a gate electrode pattern, a multilayer structure by sequentially depositing a doped polysilicon layer, an undoped polysilicon layer and a doped polysilicon layer By forming a polysilicon pattern of the semiconductor, in the subsequent gate light oxidation process, the middle part of the polysilicon layer is oxidized to suppress the blow-up phenomenon, thereby improving the profile of the gate electrode pattern. A method of forming a gate electrode pattern of a device.
최근 게이트전극 물질로서 폴리실리콘 상부에 비저항이 낮으면서도 고온에서 사용가능한 텅스텐(W), 티타늄(Ti), 탄탈륨(Ta) 등의 고융점 금속을 추가한 금속 게이트전극을 형성하고 있으며, 그 중에서도 텅스텐을 사용한 금속 게이트는 소자의 고집적화에 따른 신호처리 속도 개선의 측면에서 기존 폴리사이드 게이트전극을 대체하고 있는 실정에 있다.Recently, as gate electrode materials, metal gate electrodes including tungsten (W), titanium (Ti), and tantalum (Ta) such as tungsten (W), titanium (Ti), and tantalum (Ta), which can be used at a high temperature but have a low specific resistance, are formed. Metal gate using is in place of the existing polyside gate electrode in terms of improving the signal processing speed according to the high integration of the device.
도 1은 종래 반도체소자의 게이트전극 형성방법에 의해 형성된 게이트전극의 문제점을 설명하기 위해 나타낸 단면도이다.1 is a cross-sectional view illustrating a problem of a gate electrode formed by a gate electrode forming method of a conventional semiconductor device.
도 1에 도시된 바와 같이, 반도체기판(10) 상에 게이트산화막(20), 폴리실리콘막(30), 금속질화막(40) 및 금속층(50)을 순차적으로 적층한 후, 노광공정 및 식각 공정에 의해 게이트전극이 패터닝되어 게이트전극 패턴(70)이 형성된다.As shown in FIG. 1, after the gate oxide film 20, the polysilicon film 30, the metal nitride film 40, and the metal layer 50 are sequentially stacked on the semiconductor substrate 10, an exposure process and an etching process are performed. The gate electrode is patterned to form a gate electrode pattern 70.
그러나, 상기 금속 게이트전극 패터닝 식각 공정 시, 하부 게이트산화막과 폴리실리콘막의 에지영역에 첨점이 발생하여 전하게 집중되어, 상기 게이트산화막을 통하여 게이트전극 패턴과 드레인 사이에 누설전류가 발생되는 문제점이 있었다.However, during the metal gate electrode patterning etching process, a peak is generated in the edge regions of the lower gate oxide layer and the polysilicon layer and is concentrated completely, so that a leakage current is generated between the gate electrode pattern and the drain through the gate oxide layer.
그리하여, 상기 문제점을 해결하기 위해 폴리실리콘막을 선택산화(Selective oxidation)공정을 실시하여 상기 폴리실리콘막의 에지영역에 발생된 첨점을 제거하였다.Thus, in order to solve the problem, the polysilicon film was subjected to a selective oxidation process to remove the debris generated in the edge region of the polysilicon film.
그런데, 상기 종래와 같은 방법을 이용하게 되면 상기 선택산화 시, 폴리실리콘막 상부의 금속층의 누르는 힘에 의해 폴리실리콘 상부의 산화를 억제되고, 상기 게이트전극 패턴 식각 공정 시, 식각가스인 카본(Caborn) 계열의 불순물이 잔류되어 폴리실리콘 하부의 산화가 억제되어 "A"와 같이 폴리실리콘 중앙부분만 산화되어 볼록하게 블로우업(blow-up)현상이 발생되는 문제점이 있었다.However, when the conventional method is used, oxidation of the upper portion of the polysilicon is suppressed by the pressing force of the metal layer on the polysilicon layer during the selective oxidation, and carbon, which is an etching gas, is used during the gate electrode pattern etching process. ) Impurities of the polysilicon are suppressed and oxidation of the lower portion of the polysilicon is suppressed, so that only a central portion of the polysilicon is oxidized, such as "A", and convex blow-up occurs.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 게이트전극 패턴 중 폴리실리콘층 증착 시, 도프트 폴리실리콘층, 언도프트 폴리실리콘층 및 도프트 폴리실리콘층을 순차적으로 증착하여 다층구조의 폴리실리콘 패턴을 형성함으로써, 후속 게이트 라이트 산화 공정 시, 폴리실리콘막의 중간부분이 산화되어 블로우업(blow-up)현상이 발생하는 것을 억제하여 게이트전극 패턴의 프로파일을 개선하는 것이 목적이다.The present invention has been made to solve the above problems, an object of the present invention is to sequentially deposit the doped polysilicon layer, the undoped polysilicon layer and the doped polysilicon layer during the deposition of the polysilicon layer of the gate electrode pattern By depositing a polysilicon pattern having a multi-layer structure, it is possible to suppress the blow-up phenomenon by oxidizing the middle portion of the polysilicon film during the subsequent gate light oxidation process, thereby improving the profile of the gate electrode pattern. Purpose.
도 1은 종래 반도체소자의 게이트전극 형성방법에 의해 형성된 게이트전극의 문제점을 설명하기 위해 나타낸 단면도이다.1 is a cross-sectional view illustrating a problem of a gate electrode formed by a gate electrode forming method of a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명에 따른 반도체소자의 게이트전극 패턴 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2C are cross-sectional views sequentially illustrating a method of forming a gate electrode pattern of a semiconductor device according to the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
100 : 반도체 기판 110 : 필드산화막100 semiconductor substrate 110 field oxide film
120 : 게이트산화막 130 : 제1도프트 폴리실리콘층120: gate oxide film 130: first doped polysilicon layer
133 : 언도프트 폴리실리콘층 136 : 제2도프트 폴리실리콘층133: undoped polysilicon layer 136: second dope polysilicon layer
139 : 다층 폴리실리콘 패턴 140 : 금속질화막139: multilayer polysilicon pattern 140: metal nitride film
150 : 금속층 160 : 보호마스크150: metal layer 160: protective mask
170 : 산화 200 : 게이트전극 패턴170 oxide 200 gate electrode pattern
상기 목적을 달성하기 위하여, 본 발명은 필드산화막이 형성된 반도체기판 상에 게이트산화막을 적층한 후, 제1도프트 폴리실리콘층, 언도프트 폴리실리콘층 및 제2도프트 폴리실리콘층을 순차적으로 적층하는 다층 폴리실리콘 패턴을 형성하는 단계와; 상기 다층 폴리실리콘 패턴이 형성된 결과물 상에 금속질화막, 금속층 및 보호마스크를 순차적으로 적층한 후, 식각 공정을 진행하여 게이트전극 패턴을 형성하는 단계와; 상기 다층 폴리실리콘 패턴에 선택산화공정을 진행하여 다층 폴리실리콘 패턴 측벽을 산화시킨 후, 열공정을 진행하여 상기 언도프트 폴리실리콘층을 도프트화 시키는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 게이트전극 패턴 형성방법을 제공한다.In order to achieve the above object, the present invention, after laminating a gate oxide film on a semiconductor substrate on which a field oxide film is formed, sequentially stacking a first undoped polysilicon layer, an undoped polysilicon layer, and a second dope polysilicon layer Forming a multi-layer polysilicon pattern; Sequentially depositing a metal nitride film, a metal layer, and a protective mask on the resultant product on which the multilayer polysilicon pattern is formed, and then performing a etching process to form a gate electrode pattern; Performing a selective oxidation process on the multilayer polysilicon pattern to oxidize the sidewall of the multilayer polysilicon pattern, and then performing a thermal process to dope the undoped polysilicon layer. A method of forming an electrode pattern is provided.
본 발명은 상기 다층구조의 폴리실리콘 패턴을 형성 시, 패턴의 상부와 하부는 도프트 폴리실리콘층으로 구성하는 것을 특징으로 한다.The present invention is characterized in that when forming the polysilicon pattern of the multilayer structure, the upper and lower portions of the pattern is composed of a doped polysilicon layer.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 반도체소자의 게이트전극 패턴 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2C are cross-sectional views sequentially illustrating a method of forming a gate electrode pattern of a semiconductor device according to the present invention.
도 2a에 도시된 바와 같이, 필드산화막(110)이 형성된 반도체기판(100) 상에 게이트산화막(120)을 적층한 후, 제1도프트 폴리실리콘층(130), 언도프트 폴리실리콘층(133) 및 제2도프트 폴리실리콘층(136)을 순차적으로 적층하여 다층으로 이루어진 다층 폴리실리콘 패턴(139)을 형성한다.As shown in FIG. 2A, after the gate oxide film 120 is stacked on the semiconductor substrate 100 on which the field oxide film 110 is formed, the first undoped polysilicon layer 130 and the undoped polysilicon layer 133 are formed. ) And the second doped polysilicon layer 136 are sequentially stacked to form a multilayer polysilicon pattern 139 having a multilayer.
이때, 상기 다층 폴리실리콘 패턴(139) 형성 시, 패턴의 상부와 하부는 반드시 도프트 폴리실리콘층(130, 136)으로 구성되어야 하며, 상기 언도프트 폴리실리콘층(133)은 5∼200Å의 두께로 증착한다.In this case, when the multilayer polysilicon pattern 139 is formed, the upper and lower portions of the pattern must be composed of doped polysilicon layers 130 and 136, and the undoped polysilicon layer 133 has a thickness of 5 to 200Å. To be deposited.
또한, 상기 다층 폴리실리콘 패턴(139)은 인-스튜 또는 익스-스튜 중 어느 방법을 사용하는 것이 가능하다.In addition, the multilayer polysilicon pattern 139 may use any method of in-stud or ex-stud.
이어, 도 2b에 도시된 바와 같이, 상기 다층 폴리실리콘 패턴(139)이 형성된 결과물 상에 금속질화막(140), 금속층(150) 및 보호마스크(160)를 순차적으로 적층한 후, 식각 공정을 진행하여 게이트전극 패턴(200)을 형성한다.Subsequently, as illustrated in FIG. 2B, the metal nitride layer 140, the metal layer 150, and the protective mask 160 are sequentially stacked on the resultant product on which the multilayer polysilicon pattern 139 is formed, and then an etching process is performed. The gate electrode pattern 200 is formed.
계속하여, 도 2c에 도시된 바와 같이, 상기 다층 폴리실리콘 패턴(139)에 선택산화공정을 진행하여 다층 폴리실리콘 패턴(139) 측벽을 산화시킨다.Subsequently, as illustrated in FIG. 2C, a selective oxidation process is performed on the multilayer polysilicon pattern 139 to oxidize sidewalls of the multilayer polysilicon pattern 139.
이때, 상기 다층 폴리실리콘 패턴(139)은 상부와 하부는 산화속도가 빠른 도프트 폴리실리콘층(130, 136)으로 이루어지고, 중간부분은 산화속도가 느린 언도프트 폴리실리콘층(133)으로 구성되어 있어서 선택산화 시, 상기 다층 폴리실리콘 패턴(139)의 측벽이 균일하게 산화(170)된다.At this time, the multi-layer polysilicon pattern 139 is composed of a doped polysilicon layer (130, 136) of the upper and lower portion is a fast oxidation rate, the middle portion is composed of an undoped polysilicon layer 133 is a slow oxidation rate When the selective oxidation is performed, sidewalls of the multilayer polysilicon pattern 139 are uniformly oxidized 170.
그리고, 상기 선택산화공정을 진행한 게이트전극 패턴(200)에 580∼1050℃의 온도에서 2∼30분 동안 열공정을 진행하여 상기 언도프트 폴리실리콘층(133)을 도프트화 시킨다.In addition, the undoped polysilicon layer 133 is doped by performing a thermal process on the gate electrode pattern 200 subjected to the selective oxidation process at a temperature of 580 to 1050 ° C. for 2 to 30 minutes.
따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 게이트전극 패턴형성방법을 이용하게 되면, 게이트전극 패턴 중 폴리실리콘층 증착 시, 도프트 폴리실리콘층, 언도프트 폴리실리콘층 및 도프트 폴리실리콘층을 순차적으로 증착하여 다층구조의 폴리실리콘 패턴을 형성함으로써, 후속 게이트 라이트 산화 공정 시, 폴리실리콘막의 중간부분이 산화되어 블로우업(blow-up)현상이 발생하는 것을 억제하여 게이트전극 패턴의 프로파일을 개선할 수 있다.Therefore, as described above, when the method for forming the gate electrode pattern of the semiconductor device according to the present invention is used, the doped polysilicon layer, the undoped polysilicon layer, and the doped polysilicon are deposited when the polysilicon layer is deposited among the gate electrode patterns. By sequentially depositing layers to form a polysilicon pattern having a multi-layer structure, in the subsequent gate light oxidation process, the middle portion of the polysilicon film is oxidized to suppress blow-up phenomenon, thereby preventing the profile of the gate electrode pattern. Can be improved.
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| JPS63271971A (en) * | 1987-04-28 | 1988-11-09 | Matsushita Electric Ind Co Ltd | Mos type semiconductor device and manufacture thereof |
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| JPS63271971A (en) * | 1987-04-28 | 1988-11-09 | Matsushita Electric Ind Co Ltd | Mos type semiconductor device and manufacture thereof |
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