JPS6158257A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6158257A JPS6158257A JP17827684A JP17827684A JPS6158257A JP S6158257 A JPS6158257 A JP S6158257A JP 17827684 A JP17827684 A JP 17827684A JP 17827684 A JP17827684 A JP 17827684A JP S6158257 A JPS6158257 A JP S6158257A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- mask
- layer
- electrode layer
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置の製造方法に係り、特に半導体装
置のゲート電極、配線電極等の形成に使用されるもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and is particularly used for forming gate electrodes, wiring electrodes, etc. of a semiconductor device.
ゲート電極、配線電極等に重ね合わせ構造を有する半導
体装置の製造は従来法のように行なっていた。Semiconductor devices having a superimposed structure on gate electrodes, wiring electrodes, etc. have been manufactured using conventional methods.
すなわち、第1図(a)〜(C)、および第2図(a)
〜(C)に連続して示されるように、まず、シリコン基
板(101)の1主面に形成されたゲート酸化膜(10
2)上にポリシリコン等の電極M(103)を形成する
(第1図(a))、次に、前記電極層(103)上にレ
ジストマスク(104)を形成しく図(b))、この電
極層(103)にエツチングを施して第1の電極層(1
13)に形成する(図(c))、なお、このエツチング
によってゲート酸化膜(102)も若干エツチングされ
る。That is, FIGS. 1(a) to (C) and FIG. 2(a)
As shown in succession in (C), first, a gate oxide film (10
2) Form an electrode M (103) made of polysilicon or the like thereon (FIG. 1(a)), then form a resist mask (104) on the electrode layer (103) (FIG. 1(b)); This electrode layer (103) is etched to form a first electrode layer (103).
13) (FIG. (c)). Note that this etching also slightly etches the gate oxide film (102).
ついで、上記第1の電極層(113)をマスクにしてゲ
ート酸化膜(102)をエツチング除去する(第2図(
a))、このエツチングにより一旦ゲート酸化膜を除去
することが目的であるが、この際第1の電極の下のゲー
ト酸化膜もエツチングされて図示の如きゲート酸化膜(
112)になる1次に、シリコン基板(101)の露出
した部分を酸化させて第2のゲート酸化膜(112)を
形成(図(b)) した上にポリシリコンの第2の電極
(105)を形成する(図(C))。Next, using the first electrode layer (113) as a mask, the gate oxide film (102) is removed by etching (see FIG.
a)) The purpose of this etching is to temporarily remove the gate oxide film, but at this time, the gate oxide film under the first electrode is also etched, leaving a gate oxide film as shown in the figure (
112) Next, the exposed portion of the silicon substrate (101) is oxidized to form a second gate oxide film (112) (Figure (b)), and then a polysilicon second electrode (105) is formed. ) is formed (Figure (C)).
上記ゲート酸化膜(102)に対するエツチング後に第
2のゲート酸化膜(112)を形成した際、第1の電極
の周辺部が押し上げられる。そして1次に被着形成され
る第2の電極は第2図(C)に示すように一部が第1の
電極の下方に食い込むようになる。When the second gate oxide film (112) is formed after etching the gate oxide film (102), the peripheral portion of the first electrode is pushed up. As shown in FIG. 2(C), a portion of the second electrode that is formed as a primary layer digs into the lower part of the first electrode.
上記第1の電極の周辺が持ち上がることにより、この第
1の電極の下方に形成されている拡散層の電位が腋部で
深くなり、電位のポケットを形成し。As the periphery of the first electrode is lifted, the potential of the diffusion layer formed below the first electrode becomes deeper in the armpit, forming a potential pocket.
例えばCODのように、電荷を順次転送するようなデバ
イスにおいては、この電位のポケットによる電荷の転送
不良を起すこと、および、第2の電極の第1の電極下方
への食い込みは電界集中を生じて耐圧劣化を招くことが
あげられる。For example, in a device such as a COD that transfers charge sequentially, this potential pocket causes charge transfer failure, and the digging of the second electrode below the first electrode causes electric field concentration. This may lead to deterioration in voltage resistance.
この発明は上記従来の半導体装置の製造方法における電
極周辺の持ち上りを防止するように製造方法を改良する
。The present invention improves the manufacturing method of the conventional semiconductor device so as to prevent lifting around the electrodes.
この発明にかかる半導体装置の製造方法は、写真蝕刻に
より電極層を形成し、ついで前記写真蝕刻のマスクによ
り電極層に等方的にエツチングを施してマスクの周辺か
ら後退させたのちマスクを除去し、ついで電極表面を酸
化させる段階を含むことを特徴とする。The method for manufacturing a semiconductor device according to the present invention includes forming an electrode layer by photolithography, etching the electrode layer isotropically using the photoetching mask to retreat from the periphery of the mask, and then removing the mask. , and then oxidizing the electrode surface.
以下、この発明を一実施例につき第1図を参照して工程
順に説明する。なお、工程中東1図(a)〜(C)によ
って示される工程は従来と変わらないので説明を省略す
る。また、各図中、従来と変わらない部材については同
じ符号を付して示し、説明を省略する。Hereinafter, one embodiment of the present invention will be explained in order of steps with reference to FIG. 1. It should be noted that the steps shown in FIGS. 1A to 1C are the same as those of the conventional process, so the explanation thereof will be omitted. Further, in each figure, members that are the same as those in the conventional system are designated by the same reference numerals, and explanations thereof will be omitted.
第1図(d)は図(b)に示した第1の電極層形成に用
いたマスク(104)を残したままでこの第1の電極層
(113)を等方的にエツチングを施し第1の電極層(
3)に形成される。このエツチングは第1の電極層(1
13)の端部がマスク(104)の端面よりも所定に後
退するように1例えばフレオンを用いるケミカルドライ
エツチングで達成される。FIG. 1(d) shows that the first electrode layer (113) is isotropically etched while leaving the mask (104) used for forming the first electrode layer shown in FIG. 1(b). electrode layer (
3) is formed. This etching is performed on the first electrode layer (1
This is achieved by chemical dry etching using Freon, for example, so that the end of the mask (104) is set back to a predetermined distance from the end face of the mask (104).
次に、前記マスク(104)を除去し、第1の電極層(
113)の表面を酸化させ(図(e))、ゲート酸化膜
(2)にエツチングを施し、シリコン基板(101)の
表面を露出させる(図(f))。Next, the mask (104) is removed and the first electrode layer (
The surface of the silicon substrate (101) is oxidized (FIG. (e)), and the gate oxide film (2) is etched to expose the surface of the silicon substrate (101) (FIG. (f)).
ついで、加熱を施して新たなゲート酸化膜(12)を形
成しく図(g))、第2の電極層(5)を被着形成する
(図(h))。Next, heating is applied to form a new gate oxide film (12) (Figure (g)), and a second electrode layer (5) is deposited (Figure (h)).
この発明によれば、第1の電極を形成後、これを等方的
にエツチングし1周囲を酸化させ(図(e))だのちに
ゲート酸化膜をエツチングすることにより第1の電極下
の酸化膜がエツチングされるのを防いでいる。これによ
り、従来用1の電極(ポリシリコン)層の下面にシリコ
ン単結晶よりも遥かに高速で成長する酸化シリコン膜と
シリコン単結晶の基板露出面に成長する酸化シリコン膜
とによって第1の電極層の周辺部が持ち上げられていた
のが完全に改良された。従って第1の電極層の下方に電
位のポケットを生ずるのが防止でき、また、第2の電極
層が第1の電極層の下方への食い込みがなくなるので電
界集中による耐圧劣化が防止できるなどの顕著な効果が
ある。According to this invention, after forming the first electrode, it is isotropically etched to oxidize the surrounding area (Fig. This prevents the oxide film from being etched. As a result, the first electrode is formed by a silicon oxide film that grows on the lower surface of the conventional 1 electrode (polysilicon) layer at a much faster rate than silicon single crystal, and a silicon oxide film that grows on the exposed surface of the silicon single crystal substrate. The raised periphery of the layer has been completely improved. Therefore, it is possible to prevent potential pockets from being generated below the first electrode layer, and since the second electrode layer does not dig into the bottom of the first electrode layer, it is possible to prevent breakdown voltage deterioration due to electric field concentration. It has a remarkable effect.
次に、この発明は実施にあたって製造工程の延長はほと
んど無視してよい程度に簡単に実用に供しうる効果もあ
る。Next, the present invention has the advantage that it can be easily put into practical use to the extent that the extension of the manufacturing process can be almost ignored.
第1図はこの発明の1実施例の半導体装置の製造におけ
る電極形成工程を示す断面図、第2図は従来の半導体装
置の製造における電極形成工程の一部を示す断面図であ
る。FIG. 1 is a sectional view showing an electrode forming process in manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a part of an electrode forming process in manufacturing a conventional semiconductor device.
Claims (1)
工程と、この電極膜を写真蝕刻し電極層を形成する工程
と、前記写真蝕刻のマスクによって電極層に等方性のエ
ッチングを施したのちマスクを除去する工程と、前記電
極層表面を酸化させる工程を含む半導体装置の製造方法
。A step of forming an electrode film on a semiconductor substrate via an electrical insulating layer, a step of photo-etching the electrode film to form an electrode layer, and isotropically etching the electrode layer using the photo-etching mask. A method for manufacturing a semiconductor device, including a step of subsequently removing a mask, and a step of oxidizing the surface of the electrode layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17827684A JPS6158257A (en) | 1984-08-29 | 1984-08-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17827684A JPS6158257A (en) | 1984-08-29 | 1984-08-29 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6158257A true JPS6158257A (en) | 1986-03-25 |
Family
ID=16045639
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17827684A Pending JPS6158257A (en) | 1984-08-29 | 1984-08-29 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6158257A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01280336A (en) * | 1988-05-06 | 1989-11-10 | Nec Corp | Manufacture of semiconductor device |
US10550458B2 (en) | 2008-05-14 | 2020-02-04 | Arcelormittal | Method for producing a coated metal strip having an improved appearance |
-
1984
- 1984-08-29 JP JP17827684A patent/JPS6158257A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01280336A (en) * | 1988-05-06 | 1989-11-10 | Nec Corp | Manufacture of semiconductor device |
US10550458B2 (en) | 2008-05-14 | 2020-02-04 | Arcelormittal | Method for producing a coated metal strip having an improved appearance |
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