JPS60254751A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60254751A JPS60254751A JP11181584A JP11181584A JPS60254751A JP S60254751 A JPS60254751 A JP S60254751A JP 11181584 A JP11181584 A JP 11181584A JP 11181584 A JP11181584 A JP 11181584A JP S60254751 A JPS60254751 A JP S60254751A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- thickness
- poly
- oxidized
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法であって、ポリシリコン
の酸化・速度が不純物濃度に影響されることに基づいて
、ポリシリコン配線後の1!!Iへをなくし、平坦化で
きる半導体装置の製造方法に関するものである。Detailed Description of the Invention [Industrial Application Field] The present invention is a method for manufacturing a semiconductor device, and is based on the fact that the oxidation rate of polysilicon is affected by the impurity concentration. ! ! The present invention relates to a method of manufacturing a semiconductor device that can eliminate I and can be planarized.
従来のポリシリコンによる配線を第2図に示しており、
シリコン基板1上に薄いSin、膜2を形成した後、配
線層となるポリシリコン層3を形成し、ポリシリコン配
線形成部分にホトレジスト4を形成する(図(α))。Figure 2 shows conventional polysilicon wiring.
After forming a thin Sin film 2 on a silicon substrate 1, a polysilicon layer 3 which will become a wiring layer is formed, and a photoresist 4 is formed in the area where the polysilicon wiring is to be formed (FIG. (α)).
次にホトレジスト4を中スフとしてポリシリコン層3を
エツチングしく図(b))、次に、ホトレジスト4を除
去後、熱酸化を行い、基板1の表面及びポリシリコン3
の表面に酸化膜5.6を形成する。このとき、ポリシリ
コン3は図示の3′の部分が残る(図(C))。このよ
うにして得られた基板表面には、ポリシリコン配線形成
(3′の部分)に伴う凹凸が生じているから、図Cd)
において、At等の配線7に一形成した時、段差部8で
、断線するという欠点がある。Next, the polysilicon layer 3 is etched using the photoresist 4 as an intermediate layer (Fig.
An oxide film 5.6 is formed on the surface. At this time, a portion 3' of the polysilicon 3 shown in the figure remains (FIG. (C)). The surface of the substrate obtained in this way has irregularities due to the formation of polysilicon wiring (part 3') (Fig. Cd).
However, there is a drawback that when a wiring 7 made of At or the like is formed, the wire breaks at the stepped portion 8.
本発明はポリシリコン配線後の凹凸をなくし、平坦化が
できる半導体装置の製造方法を提供しょうとするもので
ある。The present invention aims to provide a method for manufacturing a semiconductor device that can eliminate unevenness after polysilicon wiring and can achieve planarization.
本発明(;おいては、基板上Cニボリシリコン層を形成
し、このポリシリコン層に所定パターンの膜厚の厚い部
分と薄い部分とを形成し、該薄い部分に選択的に不純物
をドープし、その後ポリシリコン層を酸化せしめ、ポリ
シリコンの酸化速度が不純物濃度に影響されることを利
用して、膜厚の薄い部分を酸化物に変えるとともに、膜
厚の厚い部分はポリシリコンの部分が残るように酸化し
、酸化後C二おける基板表面を平坦化する。In the present invention (;), a C-nivolisilicon layer is formed on a substrate, a thick part and a thin part are formed in a predetermined pattern on this polysilicon layer, and the thin part is selectively doped with an impurity, The polysilicon layer is then oxidized, and by taking advantage of the fact that the oxidation rate of polysilicon is affected by the impurity concentration, the thinner parts of the film are converted to oxide, while the thicker parts remain as polysilicon. After the oxidation, the surface of the substrate at C2 is flattened.
ポリシリコンを部分的に不純物でドープし、不純物濃度
に差ができると、不純物濃度の高い部分の方が酸化速度
が大きくなる。したがって、上記パターン以外の部分が
全て酸化されても、パターン部分にはポリシリコン層が
残る。ポリシリコンは酸化されると酸化膜厚は2倍にな
るので、これを考慮して設計すれば、酸化後の基板表面
を平坦化することができる。When polysilicon is partially doped with impurities to create a difference in impurity concentration, the oxidation rate is higher in the areas with higher impurity concentrations. Therefore, even if all parts other than the pattern are oxidized, the polysilicon layer remains in the pattern part. When polysilicon is oxidized, the oxide film thickness doubles, so if this is taken into consideration when designing, the surface of the substrate after oxidation can be flattened.
第1図(一実施例な示しており、図(α)のように、ま
ず基板11の全面にポリ5i13(厚さt)をつ(九レ
ジスト14で必要なパターンを形成する。なお、12は
下地の酸化膜である。そして、次(二図(A)で、ポリ
5i15.を全厚の1/3程度エツチングする。さらに
、図(O)でレジスト14をそのままマスクにして、不
純物(例えばリン)をイオン注入等でドープする。こう
すると、ポリSi 13のパターンを必要とする部分に
はドープされず、他の部分にだけドープされ、不純物濃
度に差ができる。ドープする量としては、ドープされる
部分の濃度がピーク値で1Q am 程度になるよう(
=する。イオン注入のドーズ量としては10111i〜
1016CrrL−2程度になる。FIG. 1 (shows one example) As shown in FIG. is the underlying oxide film. Then, as shown in Figure 2 (A), the poly 5i15. For example, phosphorus) is doped by ion implantation.In this way, the portions of the poly-Si 13 that require a pattern are not doped, but only other portions are doped, creating a difference in impurity concentration.The amount of doping is , so that the concentration of the doped part is about 1Q am at the peak value (
= do. The dose of ion implantation is 10111i~
It will be about 1016CrrL-2.
次に酸化をしてやると、不純物濃度の高い部分の方が約
2倍酸化速度が大きいので、パターン以外の部分が全て
酸化されても、パターン部分にはポリS番層16′が残
る(図(d))。酸化は、例えば1000℃位の熱酸化
である。ボ9Siは酸化されると酸化膜厚は2倍になる
ので、厚さ2/3tのポリ1si1sが酸化される部分
での酸化膜15は4/3t(ポリSiの下地の酸化膜1
2は考えない)、一方この時、パターン部分で厚さ1t
だけポリSiが酸化され、酸この後、図(−)のごとく
、従来と同じくコンタクト穴18を形成し、At配線1
7のパターニングを行う。本実施例によれば、Atパタ
ーンの断線は完全に防止できる。Next, when oxidation is performed, the oxidation rate is about twice as high in areas with a high impurity concentration, so even if all areas other than the pattern are oxidized, the poly S number layer 16' remains in the pattern area (Fig. d)). The oxidation is, for example, thermal oxidation at about 1000°C. When the silicon substrate 9Si is oxidized, the oxide film thickness doubles, so the oxide film 15 in the area where the 2/3t thick poly 1si1s is oxidized is 4/3t (the oxide film 1 on the base of the polySi).
2 is not considered), on the other hand, at this time, the thickness of the pattern part is 1t.
After that, as shown in the figure (-), a contact hole 18 is formed as in the conventional method, and the At wiring 1 is oxidized.
Perform patterning in step 7. According to this embodiment, disconnection of the At pattern can be completely prevented.
以上、本発明について一実施例を示したが、本発明はポ
リシリコンを用いる集積回路製造に広く適用できる。Although one embodiment of the present invention has been described above, the present invention can be widely applied to the manufacture of integrated circuits using polysilicon.
本発明によれば、ポリシリコンの酸化速度が不純物濃度
の増加と共に大きくなることを利用し、ポリシリコンの
パターン形成後の凹凸をなくすことができ、アルミパタ
ーン形成時の断線を防ぐことができる利点がある。According to the present invention, by utilizing the fact that the oxidation rate of polysilicon increases as the impurity concentration increases, it is possible to eliminate unevenness after forming a polysilicon pattern, and advantageously, it is possible to prevent wire breakage when forming an aluminum pattern. There is.
第1図は本発明の半導体装置の製造方法の一実施例の工
程図、
第2図は従来の半導体装置の製造方法の工程図。
(主なる符号)
11・・・基板
12・・・下地の酸化膜
13・・・ポリS寥
14・・・レジスト
15・・・酸化膜
17・・・At配線
18・・・コンタクト穴
特許出願人 富士通株式会社
代理人 弁理士 玉蟲久五部(外1名)第1図
第2図FIG. 1 is a process diagram of an embodiment of the semiconductor device manufacturing method of the present invention, and FIG. 2 is a process diagram of a conventional semiconductor device manufacturing method. (Main symbols) 11... Substrate 12... Base oxide film 13... Polysilicon layer 14... Resist 15... Oxide film 17... At wiring 18... Contact hole patent application Person Fujitsu Limited Agent Patent Attorney Gobe Tamamushi (1 other person) Figure 1 Figure 2
Claims (1)
に所定パターンの膜厚の厚い部分と薄い部分とを形成し
、該薄い部分に選択的に不純物をドープし、その後ポリ
シリコン層を酸化せしめ、ポリシリコンの酸化速度が不
純物濃度に影響されることを利用して、膜厚の薄い部分
を酸化物に変えるととも(=、膜厚の厚い部分はポリシ
リコンの部分が残るように酸化し、酸化後における基板
表面を平坦化することを特徴とする半導体装置の製造方
法。On the substrate (form a polysilicon layer, form a thick part and a thin part in a predetermined pattern on the polysilicon layer, selectively dope impurities into the thin part, and then oxidize the polysilicon layer) By taking advantage of the fact that the oxidation rate of polysilicon is affected by the impurity concentration, we change the thin part of the film to oxide (=, the thick part is oxidized so that the polysilicon part remains). and flattening the surface of the substrate after oxidation.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11181584A JPS60254751A (en) | 1984-05-31 | 1984-05-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11181584A JPS60254751A (en) | 1984-05-31 | 1984-05-31 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60254751A true JPS60254751A (en) | 1985-12-16 |
Family
ID=14570848
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11181584A Pending JPS60254751A (en) | 1984-05-31 | 1984-05-31 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60254751A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62299050A (en) * | 1986-06-18 | 1987-12-26 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
-
1984
- 1984-05-31 JP JP11181584A patent/JPS60254751A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62299050A (en) * | 1986-06-18 | 1987-12-26 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
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