JPH0260167A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device of an excellent electrical property by a method wherein a MOS semiconductor device is composed of a first and a second semiconductor layer and a gate electrode, where the first semiconductor layer and the gate electrode are overlapped with each other by a specified amount. CONSTITUTION:First semiconductor layers 102 and 302, which are to be a source and a drain region respectively, and second semiconductor layers 103 and 303, which are to be a sources drain and a channel region respectively, are formed on an insulating substrate 101. Moreover, gate electrodes 105 and 305 are formed thereon through the intermediary of an insulating layer 104, and a contact hole 306 which serves as an electrode lead-out section is provided thereon too. And, the layers 102 and 302 and the electrodes 105 and 305 are so formed as to overlap each other by a length of 2-4mum. When the overlapped length of the layer 302 with the electrode 305 is equal to 2mum or less, an ON-current of a MOS semiconductor device TFT decreases sharply, and when the overlapped length exceeds 2mum, the ON-current also decreases. By this setup, a TFT excellent in an electrical property can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type semiconductor device formed on an insulating substrate or an insulating film.

[Prior Art] Conventionally, it has been known that in a MOS type semiconductor device (hereinafter abbreviated as TPT) formed on an insulating substrate or an insulating film, the thinner the thickness of the semiconductor layer in the channel portion, the better the electrical characteristics thereof. . On the other hand, in order to have a low resistance value in the source/drain regions, the semiconductor layer in these regions needs to have a certain thickness. However, since the channel part and the source/drain regions are usually formed of a single semiconductor layer formed at the same time, two conditions are met: the semiconductor layer in the channel part is thin and the semiconductor layer in the source/drain regions is thick. cannot be fulfilled at the same time. Therefore, in the prior art, a structure shown in FIG. 2 has been proposed as a method that satisfies the above two conditions.

In FIG. 2, 201 is an insulating substrate, 202 and 202
203 is a first semiconductor layer made of highly impurity-doped, low-resistance polysilicon to become the source/drain, and 203 is polysilicon or the like which overlaps the source/drain region and forms a channel layer. 204 is a gate insulating film, and 205 is a gate electrode made of polysilicon or the like. A feature of the structure shown in FIG. 2 is that the semiconductor layer in the channel portion can be made as thin as possible and thick enough to have a sufficiently low resistance value of the semiconductor layer serving as the source/drain region.

[Problems to be Solved by the Invention] The conventional structure shown in FIG. 2 has a structure in which the semiconductor layer in the channel portion is made as thin as possible and thick enough to sufficiently lower the resistance value of the semiconductor layer that becomes the source/drain region. can do. However, the above structure has a problem in that the electrical characteristics of the TPT cannot necessarily be improved.

That is, in FIG. 2, since the gate electrode 205 and the first semiconductor layer 202, 202', which should become the source/drain, do not overlap, the film thickness of a part of the source/drain region becomes thinner. The problem is that the resistance value of the region becomes high and a sufficient ON current cannot be obtained. Therefore, an object of the present invention is to solve the above-mentioned problems in a structure in which the semiconductor layer in the channel region is made as thin as possible and is formed thick enough to sufficiently lower the resistance value of the semiconductor layer that becomes the source/drain region. The purpose of the present invention is to propose a structure that obtains an excellent TPT.

[Means for Solving the Problems] Means for solving the above-mentioned problems in the present invention are as follows: (1) A first semiconductor serving as a source and a drain of a MOS transistor is provided on one main surface or an insulating film of an insulating substrate. a second semiconductor layer overlapping the source and drain regions and serving as a channel region, an insulating film formed on the second semiconductor layer, and the first semiconductor layer on the insulating film. It is characterized by having a gate electrode that overlaps with the gate electrode by 2 to 4 μm.

<2. In claim 1, the first semiconductor layer,
The second semiconductor layer and the gate electrode are made of polysilicon.

[Examples] The details of the present invention will be explained based on examples. FIG. 3 is an embodiment according to the present invention, showing a plan view of a TFT device. FIG. 1 shows a cross-sectional view taken along the line X-X'' in FIG. It is a polysilicon layer with a thickness of 120% by CVD method.
Form to a thickness of 0. 103.303 is a second polysilicon layer which becomes a source/drain region and a channel region, and is formed to a thickness of 900 nm by CVD. 104
is a gate insulating film and is formed to a thickness of 1200 nm by thermal oxidation. Reference numeral 105.305 is a polysilicon layer which will become a gate electrode, and is formed to a thickness of 3500 nm using the CVD method. Reference numeral 306 is a contact hole that serves as an electrode extraction portion (the contact hole is not shown in the cross-sectional view of FIG. 1). As shown in FIG.
They overlap by μm.

The inventors have recognized that the electrical characteristics of TPT strongly depend on the amount of overlap (overlap between the first polysilicon layer and the gate electrode). Figure 4 shows the amount of overlap and O of TPT.
This shows the relationship between N current. The negative overlap amount in FIG. 4 indicates that the gate electrode 305 and the first polysilicon layers 102 to 302 are separated from each other. When the amount of overlap is smaller than 2 μm,
It can be seen that when the ON current suddenly decreases and further becomes smaller than 1 μm, the ON current becomes zero. The reason for this is as follows.

This will be explained with reference to FIG. 2, which is a sectional view of a TPT according to the prior art. The manufacturing method shown in FIG.
After forming the second polysilicon layer 203, the gate oxide film 204 is formed by thermally oxidizing the second polysilicon layer. The thickness of the second polysilicon layer is reduced by thermal oxidation, and the remaining thickness becomes a channel layer. Next, gate electrode 205 is formed from a third polysilicon layer. The cross-sectional view shown in FIG. 2 shows the process up to the formation of the third polysilicon layer. After that, in order to diffuse impurities into the source/drain regions, the gate oxide film is etched using the gate electrode as a mask. At this time, the second polysilicon layer is slightly etched and its thickness is reduced. Next, for example, when phosphorus is diffused, the thickness of the second polysilicon layer decreases. Since the second polysilicon layer becomes a channel region, it must be formed as thin as possible, and as a result, the polysilicon layer is extremely thin in the region where the gate electrode 205 and the first polysilicon layer do not overlap in FIG. Become,
In some cases, polysilicon may disappear in the region. Therefore, as shown in FIG. 4, the ON current becomes zero when the amount of overlap is negative. In the region where the amount of overlap is 0 to 2 μm, the first polysilicon and the third
Due to the misalignment of the polysilicon mask, the overlapping amount becomes substantially negative, and therefore the ON current becomes small.

The ON current decreases as the amount of overlap increases in FIG. 4 because the thick region of polysilicon in the channel portion increases.

As described above, it can be seen that if the amount of overlap between the first polysilicon serving as the source/drain and the third polysilicon serving as the gate electrode is too small or too large, the ON current of the TPT will become small.

In order to obtain the largest ON current, the amount of molding should be 2.
It is preferable to set the thickness to 4 μm.

[Effects of the Invention] According to the present invention, a TPT element with excellent electrical characteristics can be formed on a glass substrate or an insulating film.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a TPT according to the present invention. FIG. 2 is a sectional view of a TPT according to the prior art. FIG. 3 shows a TPT according to the present invention.
Top view. FIG. 4 shows the basis of the present invention, and T
FIG. 3 is a diagram showing the relationship between the parameters of the PT element structure and the electrical characteristics of the TPT. 101.201...Glass substrate 102.202.302...Polysilicon serving as source/drain 103.203.303...Polysilicon serving as channel 104.204...Gate insulating film 105.205...・Gate electrode Applicant: Seiko Epson Co., Ltd. Agent Patent attorney: Ueghi Uikan and 1 other person Overlap amount (μm)

Claims (2)

[Claims] (1) A first semiconductor layer that becomes a source and a drain of a MOS transistor on one main surface or an insulating film of an insulating substrate; a second semiconductor layer that overlaps the source and drain regions and becomes a channel region; A semiconductor device comprising: an insulating film formed on a second semiconductor layer; and a gate electrode overlapping the first semiconductor layer by 2 to 4 μm on the insulating film. (2) The semiconductor device according to claim 1, wherein the first semiconductor layer, the second semiconductor layer, and the gate electrode are made of polysilicon.