JPH0125228B2 - - Google Patents
Info
- Publication number
- JPH0125228B2 JPH0125228B2 JP56117072A JP11707281A JPH0125228B2 JP H0125228 B2 JPH0125228 B2 JP H0125228B2 JP 56117072 A JP56117072 A JP 56117072A JP 11707281 A JP11707281 A JP 11707281A JP H0125228 B2 JPH0125228 B2 JP H0125228B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- board
- wiring pattern
- lsi
- modified
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11707281A JPS5818950A (ja) | 1981-07-28 | 1981-07-28 | 多層配線基板 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11707281A JPS5818950A (ja) | 1981-07-28 | 1981-07-28 | 多層配線基板 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5818950A JPS5818950A (ja) | 1983-02-03 |
| JPH0125228B2 true JPH0125228B2 (enrdf_load_stackoverflow) | 1989-05-16 |
Family
ID=14702711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11707281A Granted JPS5818950A (ja) | 1981-07-28 | 1981-07-28 | 多層配線基板 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5818950A (enrdf_load_stackoverflow) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6135578A (ja) * | 1984-07-27 | 1986-02-20 | Agency Of Ind Science & Technol | 超電導回路の結線方法 |
| US4782193A (en) * | 1987-09-25 | 1988-11-01 | Ibm Corp. | Polygonal wiring for improved package performance |
| US5177594A (en) * | 1991-01-09 | 1993-01-05 | International Business Machines Corporation | Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55108797A (en) * | 1979-02-13 | 1980-08-21 | Hitachi Ltd | Circuit board |
| US4245273A (en) * | 1979-06-29 | 1981-01-13 | International Business Machines Corporation | Package for mounting and interconnecting a plurality of large scale integrated semiconductor devices |
-
1981
- 1981-07-28 JP JP11707281A patent/JPS5818950A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5818950A (ja) | 1983-02-03 |
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