JPH0119168B2 - - Google Patents

Info

Publication number
JPH0119168B2
JPH0119168B2 JP57089328A JP8932882A JPH0119168B2 JP H0119168 B2 JPH0119168 B2 JP H0119168B2 JP 57089328 A JP57089328 A JP 57089328A JP 8932882 A JP8932882 A JP 8932882A JP H0119168 B2 JPH0119168 B2 JP H0119168B2
Authority
JP
Japan
Prior art keywords
register
shift register
shift
instruction
logic operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57089328A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58205208A (ja
Inventor
Seishi Ochiai
Akira Shirota
Keijiro Fujita
Yukihiko Inagaki
Kaoru Ootani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Idec Corp
Original Assignee
Idec Izumi Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Idec Izumi Corp filed Critical Idec Izumi Corp
Priority to JP57089328A priority Critical patent/JPS58205208A/ja
Publication of JPS58205208A publication Critical patent/JPS58205208A/ja
Publication of JPH0119168B2 publication Critical patent/JPH0119168B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/054—Input/output

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)
  • Shift Register Type Memory (AREA)
JP57089328A 1982-05-25 1982-05-25 シーケンスコントローラのシフトレジスタ制御装置 Granted JPS58205208A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57089328A JPS58205208A (ja) 1982-05-25 1982-05-25 シーケンスコントローラのシフトレジスタ制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57089328A JPS58205208A (ja) 1982-05-25 1982-05-25 シーケンスコントローラのシフトレジスタ制御装置

Publications (2)

Publication Number Publication Date
JPS58205208A JPS58205208A (ja) 1983-11-30
JPH0119168B2 true JPH0119168B2 (enExample) 1989-04-10

Family

ID=13967604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57089328A Granted JPS58205208A (ja) 1982-05-25 1982-05-25 シーケンスコントローラのシフトレジスタ制御装置

Country Status (1)

Country Link
JP (1) JPS58205208A (enExample)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5671105A (en) * 1979-11-13 1981-06-13 Yaskawa Electric Mfg Co Ltd Shift register type programmable controller with memory

Also Published As

Publication number Publication date
JPS58205208A (ja) 1983-11-30

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