JPH01176940U - - Google Patents

Info

Publication number
JPH01176940U
JPH01176940U JP7457788U JP7457788U JPH01176940U JP H01176940 U JPH01176940 U JP H01176940U JP 7457788 U JP7457788 U JP 7457788U JP 7457788 U JP7457788 U JP 7457788U JP H01176940 U JPH01176940 U JP H01176940U
Authority
JP
Japan
Prior art keywords
frame
circuit board
semiconductor chip
ultraviolet curing
preventing leakage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7457788U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7457788U priority Critical patent/JPH01176940U/ja
Publication of JPH01176940U publication Critical patent/JPH01176940U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は考案の実施例を説明し、イは上面図、
ロは縦断面図である。第2図は考案の実施例を製
作する製法説明図である。第3図は従来例を説明
し、イ,ロ,ハはそれぞれ縦断面図である。 1…絶縁板、2…回路パターン、3…回路基板
、4…枠、5…ネガフイルム、6…紫外線、7…
スペーサー、8…ガイドピン。
Figure 1 illustrates an embodiment of the invention, and Figure 1 is a top view;
B is a vertical sectional view. FIG. 2 is an explanatory diagram of a manufacturing method for manufacturing an embodiment of the invention. FIG. 3 explains a conventional example, and A, B, and C are longitudinal cross-sectional views, respectively. 1... Insulating board, 2... Circuit pattern, 3... Circuit board, 4... Frame, 5... Negative film, 6... Ultraviolet rays, 7...
Spacer, 8...Guide pin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 回路基板の所定位置に、紫外線硬化樹脂、又は
紫外線硬化/熱硬化樹脂による半導体チツプ封止
樹脂の流出防止用枠を固着形成したことを特徴と
する半導体チツプ封止樹脂の流出防止枠付き回路
基板。
A circuit board with a frame for preventing leakage of semiconductor chip sealing resin, characterized in that a frame for preventing leakage of semiconductor chip sealing resin made of ultraviolet curing resin or ultraviolet curing/thermosetting resin is fixedly formed at a predetermined position of the circuit board. .
JP7457788U 1988-06-04 1988-06-04 Pending JPH01176940U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7457788U JPH01176940U (en) 1988-06-04 1988-06-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7457788U JPH01176940U (en) 1988-06-04 1988-06-04

Publications (1)

Publication Number Publication Date
JPH01176940U true JPH01176940U (en) 1989-12-18

Family

ID=31299682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7457788U Pending JPH01176940U (en) 1988-06-04 1988-06-04

Country Status (1)

Country Link
JP (1) JPH01176940U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5893240A (en) * 1981-11-30 1983-06-02 Japan Synthetic Rubber Co Ltd Semiconductor device and preparation thereof
JPS58127333A (en) * 1982-01-11 1983-07-29 クリテイコン・インコ−ポレイテツド Method of sealing semiconductor chip
JPS61184834A (en) * 1985-02-13 1986-08-18 Toshiba Chem Corp Manufacture of resin-molded semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5893240A (en) * 1981-11-30 1983-06-02 Japan Synthetic Rubber Co Ltd Semiconductor device and preparation thereof
JPS58127333A (en) * 1982-01-11 1983-07-29 クリテイコン・インコ−ポレイテツド Method of sealing semiconductor chip
JPS61184834A (en) * 1985-02-13 1986-08-18 Toshiba Chem Corp Manufacture of resin-molded semiconductor device

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