JPS5869955U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5869955U JPS5869955U JP16507181U JP16507181U JPS5869955U JP S5869955 U JPS5869955 U JP S5869955U JP 16507181 U JP16507181 U JP 16507181U JP 16507181 U JP16507181 U JP 16507181U JP S5869955 U JPS5869955 U JP S5869955U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor equipment
- abstract
- recorded
- lead
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の半導装置の斜視図、第2図は本考案の第
1の実施例の斜視図、第3図aは本考案の第2の実施例
の斜視図、第3図すは第3図aのA−A’線に沿って切
断しその切断面を示す断面図である。尚図において、
1′、 1“、 1“’、5,7.8・・・・・・リー
ド、2゜6・・・・・・放熱部、3・・・・・・半導体
素子固着部、4・・・・・・プラスチックモールド樹脂
のケースが設けられる部分。FIG. 1 is a perspective view of a conventional semiconductor device, FIG. 2 is a perspective view of a first embodiment of the present invention, FIG. 3a is a perspective view of a second embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along the line AA' in FIG. 3a and showing the cut surface thereof. In the figure, 1', 1", 1"', 5, 7.8...Lead, 2゜6...Heat radiation part, 3...Semiconductor element fixing part , 4... A part where a plastic mold resin case is provided.
Claims (1)
ことを特徴とする半導体装置。A semiconductor device characterized by using a lead having a folded portion within a molded resin.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16507181U JPS5869955U (en) | 1981-11-05 | 1981-11-05 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16507181U JPS5869955U (en) | 1981-11-05 | 1981-11-05 | semiconductor equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5869955U true JPS5869955U (en) | 1983-05-12 |
Family
ID=29957281
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16507181U Pending JPS5869955U (en) | 1981-11-05 | 1981-11-05 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5869955U (en) |
-
1981
- 1981-11-05 JP JP16507181U patent/JPS5869955U/en active Pending
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