JPH01165641U - - Google Patents
Info
- Publication number
- JPH01165641U JPH01165641U JP1988061374U JP6137488U JPH01165641U JP H01165641 U JPH01165641 U JP H01165641U JP 1988061374 U JP1988061374 U JP 1988061374U JP 6137488 U JP6137488 U JP 6137488U JP H01165641 U JPH01165641 U JP H01165641U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- face
- bumps
- down bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 16
- 238000003486 chemical etching Methods 0.000 claims 1
- 239000002775 capsule Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Description
第１図から第４図までが本考案に関し、第１図
は本考案によるフエースダウンボンデイング用半
導体チツプの実施例の表面図および裏面図、第２
図はこの半導体チツプのバンプおよびマークが設
けられた部分の一部拡大断面図、第３図は本考案
の異なる実施例を示す半導体チツプの裏面図、第
４図は本考案による半導体チツプの配線基板への
実装の模様を示す一部断面図である。第５図以降
は従来技術に関し、第５図は従来のフエースダウ
ンボンデイング用半導体チツプの裏面図、第６図
は半導体チツプの輸送時の状態を示す模式図であ
る。図において、
１０：半導体チツプ、１０ａ：半導体チツプ１
０の表面、１０ｂ：半導体チツプ１０の裏面、１
１：半導体チツプの基板、１２：半導体層、１３
：酸化膜、１４：接続膜、１５：保護膜、２０：
バンプ、３０〜３４：本考案によるマーク、４０
：配線基板、４１：セラミツク基板、４２：配線
導体、５０：従来のマーク、６０：輸送用カプセ
ル、６１：詰物、である。
1 to 4 relate to the present invention; FIG. 1 is a front view and a back view of an embodiment of a semiconductor chip for face-down bonding according to the present invention;
The figure is a partially enlarged sectional view of a portion of this semiconductor chip where bumps and marks are provided, Figure 3 is a back view of the semiconductor chip showing a different embodiment of the present invention, and Figure 4 is the wiring of the semiconductor chip according to the present invention. FIG. 3 is a partial cross-sectional view showing a pattern of mounting on a board. FIG. 5 and subsequent figures relate to the prior art. FIG. 5 is a back view of a conventional semiconductor chip for face-down bonding, and FIG. 6 is a schematic diagram showing the state of the semiconductor chip during transportation. In the figure, 10: semiconductor chip, 10a: semiconductor chip 1
0 surface, 10b: back surface of semiconductor chip 10, 1
1: Substrate of semiconductor chip, 12: Semiconductor layer, 13
: Oxide film, 14: Connection film, 15: Protective film, 20:
Bump, 30-34: Mark according to the present invention, 40
: Wiring board, 41: Ceramic board, 42: Wiring conductor, 50: Conventional mark, 60: Transport capsule, 61: Filling.
Claims (1)
象とフエースダウンボンデイング接続される半導
体チツプであつて、裏面側の半導体面が艷消し面
に形成され、この裏面側半導体面の周縁部の特定
個所に化学エツチングにより形成された光沢面か
らなるマークを備えたことを特徴とするフエース
ダウンボンデイング用半導体チツプ。 A semiconductor chip that has bumps on the front surface and is connected to a mounting target through face-down bonding via the bumps, the semiconductor surface on the back side is formed as a faded surface, and the semiconductor chip is bonded at a specific point on the periphery of the back side semiconductor surface. A semiconductor chip for face-down bonding characterized by having a mark made of a glossy surface formed by chemical etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988061374U JPH01165641U (en) | 1988-05-10 | 1988-05-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988061374U JPH01165641U (en) | 1988-05-10 | 1988-05-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01165641U true JPH01165641U (en) | 1989-11-20 |
Family
ID=31287047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988061374U Pending JPH01165641U (en) | 1988-05-10 | 1988-05-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01165641U (en) |
-
1988
- 1988-05-10 JP JP1988061374U patent/JPH01165641U/ja active Pending