JP7750315B2 - 電子装置及び電子装置の製造方法 - Google Patents

電子装置及び電子装置の製造方法

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Publication number
JP7750315B2
JP7750315B2 JP2023580031A JP2023580031A JP7750315B2 JP 7750315 B2 JP7750315 B2 JP 7750315B2 JP 2023580031 A JP2023580031 A JP 2023580031A JP 2023580031 A JP2023580031 A JP 2023580031A JP 7750315 B2 JP7750315 B2 JP 7750315B2
Authority
JP
Japan
Prior art keywords
substrate
bump
conductive film
convex portion
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2023580031A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2023152961A1 (https=
JPWO2023152961A5 (https=
Inventor
正壽 竹野内
悟覚 ▲高▼馬
岳明 島内
剛 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of JPWO2023152961A1 publication Critical patent/JPWO2023152961A1/ja
Publication of JPWO2023152961A5 publication Critical patent/JPWO2023152961A5/ja
Application granted granted Critical
Publication of JP7750315B2 publication Critical patent/JP7750315B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0912—Manufacture or treatment of Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/81—Containers; Mountings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/81—Containers; Mountings
    • H10N60/815—Containers; Mountings for Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • Artificial Intelligence (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2023580031A 2022-02-14 2022-02-14 電子装置及び電子装置の製造方法 Active JP7750315B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/005649 WO2023152961A1 (ja) 2022-02-14 2022-02-14 電子装置及び電子装置の製造方法

Publications (3)

Publication Number Publication Date
JPWO2023152961A1 JPWO2023152961A1 (https=) 2023-08-17
JPWO2023152961A5 JPWO2023152961A5 (https=) 2024-09-06
JP7750315B2 true JP7750315B2 (ja) 2025-10-07

Family

ID=87564009

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023580031A Active JP7750315B2 (ja) 2022-02-14 2022-02-14 電子装置及び電子装置の製造方法

Country Status (4)

Country Link
US (1) US20240389478A1 (https=)
EP (1) EP4482284A4 (https=)
JP (1) JP7750315B2 (https=)
WO (1) WO2023152961A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025046715A1 (ja) * 2023-08-28 2025-03-06 富士通株式会社 量子ビットデバイス及び量子ビットデバイスの製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000306952A (ja) 1999-04-20 2000-11-02 Nitto Denko Corp 実装用配線基板およびその製造方法
JP2003204162A (ja) 2001-10-30 2003-07-18 Dainippon Printing Co Ltd プリント配線基板、プリント配線基板用レリーフパターン付金属板、及び、プリント配線基板の製造方法
WO2005097396A1 (ja) 2004-04-08 2005-10-20 Matsushita Electric Industrial Co., Ltd. 接合方法及びその装置
JP2009231721A (ja) 2008-03-25 2009-10-08 Toppan Printing Co Ltd 半導体装置とその製造方法
WO2020169418A1 (en) 2019-02-21 2020-08-27 International Business Machines Corporation Stud bumps for post-measurement qubit frequency modification

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11163204A (ja) * 1997-11-28 1999-06-18 Fujitsu Ltd 半導体装置及びその実装構造
JP6974470B2 (ja) 2016-09-14 2021-12-01 グーグル エルエルシーGoogle LLC ローカル真空キャビティーを使用して量子デバイスの中の散逸および周波数ノイズを低減させること
US10692795B2 (en) 2018-11-13 2020-06-23 International Business Machines Corporation Flip chip assembly of quantum computing devices
US10944039B2 (en) * 2019-06-19 2021-03-09 International Business Machines Corporation Fabricating transmon qubit flip-chip structures for quantum computing devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000306952A (ja) 1999-04-20 2000-11-02 Nitto Denko Corp 実装用配線基板およびその製造方法
JP2003204162A (ja) 2001-10-30 2003-07-18 Dainippon Printing Co Ltd プリント配線基板、プリント配線基板用レリーフパターン付金属板、及び、プリント配線基板の製造方法
WO2005097396A1 (ja) 2004-04-08 2005-10-20 Matsushita Electric Industrial Co., Ltd. 接合方法及びその装置
JP2009231721A (ja) 2008-03-25 2009-10-08 Toppan Printing Co Ltd 半導体装置とその製造方法
WO2020169418A1 (en) 2019-02-21 2020-08-27 International Business Machines Corporation Stud bumps for post-measurement qubit frequency modification

Also Published As

Publication number Publication date
JPWO2023152961A1 (https=) 2023-08-17
US20240389478A1 (en) 2024-11-21
WO2023152961A1 (ja) 2023-08-17
EP4482284A4 (en) 2025-04-30
EP4482284A1 (en) 2024-12-25

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