Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
  • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
  • G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
  • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
  • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N60/00—Superconducting devices
  • H10N60/01—Manufacture or treatment
  • H10N60/0912—Manufacture or treatment of Josephson-effect devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N60/00—Superconducting devices
  • H10N60/80—Constructional details
  • H10N60/81—Containers; Mountings
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N60/00—Superconducting devices
  • H10N60/80—Constructional details
  • H10N60/81—Containers; Mountings
  • H10N60/815—Containers; Mountings for Josephson-effect devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Definitions

• the disclosed technique relates to an electronic device and a method for manufacturing the electronic device.
• a quantum computing device which includes a substrate including Josephson junctions and an interposer substrate bonded to the substrate via bumps.
• a quantum device includes a plurality of protrusions provided on the surface of a quantum bit chip and a heat sink having a plurality of depressions arranged to match the plurality of protrusions.
• Quantum devices are also known that include a substrate containing a superconducting quantum device and a cap layer bonded to the substrate to form a closed cavity therebetween.
• bonding between substrates is performed by bonding a plurality of bumps provided on one substrate to pads provided on the other substrate.
• the plurality of bumps are deformed by applying a pressing force that presses one substrate against the other substrate, and are crimped to the pads.
• the pressing force is not applied to some of the bumps that are relatively low, resulting in poor bonding in some of the bumps that are relatively low. may occur.
• the disclosed technique aims at suppressing defective bonding of bumps in an electronic device including a plurality of substrates bonded to each other via bumps.
• An electronic device includes a first substrate having a circuit element, and a second substrate laminated on the first substrate and covering the circuit element.
• One of the first substrate and the second substrate has bumps bonded to the other of the first substrate and the second substrate.
• the bump is composed of the base material of the substrate, and has a tapered projection whose cross-sectional area intersecting the stacking direction of the first substrate and the second substrate gradually decreases toward the tip.
• the bump includes a tapered conductive film that covers the surface of the protrusion and reflects the shape of the protrusion.
• FIG. 1 is a partial equivalent circuit diagram of a quantum arithmetic device according to an embodiment of technology disclosed herein;
• FIG. 1 is a diagram showing an example of a circuit configuration of a qubit element according to an embodiment of technology disclosed;
• FIG. 1 is a diagram showing an example of a connection configuration between qubit elements according to an embodiment of the disclosed technique;
• FIG. 1 is a diagram illustrating an example of a circuit configuration of a resonator according to an embodiment of technology disclosed;
• FIG. 1 is a schematic cross-sectional view showing an example of a configuration of a quantum arithmetic device according to an embodiment of technology disclosed herein;
• FIG. FIG. 4 is a plan view showing an example of a configuration of a second substrate according to an embodiment of technology disclosed herein;
• FIG. 6B is a cross-sectional view along 6B-6B in FIG. 6A;
• 1 is a perspective view showing an example of a bump structure according to an embodiment of technology disclosed herein;
• FIG. 4 is a cross-sectional view showing an example of a method of bonding bumps and pads according to an embodiment of the disclosed technology;
• FIG. 4 is a cross-sectional view showing an example of a method of bonding bumps and pads according to an embodiment of the disclosed technology;
• FIG. 4 is a diagram modeling a cone-shaped bump according to an embodiment of the disclosed technology;
• 7 is a graph showing an example of the relationship between the pressing force applied to the bump and the height of the bump according to the embodiment of the technology disclosed.
• FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a second substrate according to an embodiment of technology disclosed herein;
• FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a second substrate according to an embodiment of technology disclosed herein;
• FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a second substrate according to an embodiment of technology disclosed herein;
• FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a second substrate according to an embodiment of technology disclosed herein;
• FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a second substrate according to an embodiment of technology disclosed herein;
• FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a second substrate according to an embodiment of technology disclosed herein;
• FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a second substrate according to an embodiment of technology disclosed herein;
• FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a second substrate according to an embodiment of technology disclosed herein;
• FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a second substrate according to an embodiment of technology disclosed herein;
• FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a second substrate according to an embodiment of technology disclosed herein;
• FIG. 4A is a cross-sectional view showing an example of a method for manufacturing a first substrate according to an embodiment of technology disclosed herein;
• FIG. 4A is a cross-sectional view showing an example of a method for manufacturing a first substrate according to an embodiment of technology disclosed herein;
• FIG. 4A is a cross-sectional view showing an example of a method for manufacturing a first substrate according to an embodiment of technology disclosed herein;
• FIG. 4A is a cross-sectional view showing an example of a method for manufacturing a first substrate according to an embodiment of technology disclosed herein;
• FIG. 4A is a cross-sectional view showing an example of a method for manufacturing a first substrate according to an embodiment of technology disclosed herein;
• FIG. 4A is a cross-sectional view showing an example of a method for manufacturing a first substrate according to an embodiment of technology disclosed herein;
• FIG. 4A is a cross-sectional view showing an example of a method for manufacturing a first substrate according to an embodiment of technology disclosed herein;
• FIG. 4A is a cross-sectional view showing an example of a method for manufacturing a first substrate according to an embodiment of technology disclosed herein;
• FIG. 4A is a cross-sectional view showing an example of a method for manufacturing a first substrate according to an embodiment of technology disclosed herein;
• FIG. 4A is a cross-sectional view showing an example of a method for manufacturing a first substrate according to an embodiment of technology disclosed
• FIG. 4 is a cross-sectional view showing an example of a method for bonding a first substrate and a second substrate according to an embodiment of the disclosed technique
• FIG. 4 is a cross-sectional view showing an example of a method for bonding a first substrate and a second substrate according to an embodiment of the disclosed technique
• FIG. 10 is a cross-sectional view showing bonding between a bump and a pad according to a comparative example
• FIG. 10 is a cross-sectional view showing bonding between a bump and a pad according to a comparative example
• FIG. 7 is a cross-sectional view showing an example of a method of forming bumps according to a comparative example
• FIG. 10 is a plan view showing an example of the configuration of a second substrate according to another embodiment of the disclosed technique
• FIG. 16B is a cross-sectional view along 16B-16B in FIG. 16A
• FIG. 10 is a cross-sectional view showing an example of the configuration of a quantum arithmetic device according to another embodiment of the disclosed technique
• FIG. 1 is a plan view showing an example of the configuration of a quantum arithmetic device 10 according to an embodiment of technology disclosed.
• the quantum arithmetic device 10 has a quantum bit element (Qubit) 20 provided on a first substrate 30 , a resonator 21 and a readout electrode 22 .
• the quantum arithmetic device 10 is an example of an electronic device in technology disclosed herein.
• the qubit element 20 and the resonator 21 are examples of circuit elements in the technology disclosed.
• the qubit element 20 is an element that forms a coherent two-level system using superconductivity.
• FIG. 2 is a diagram showing an example of the circuit configuration of the quantum bit element 20.
• the quantum bit element 20 performs quantum operations using nonlinear energy, and includes a transmon quantum bit circuit in which a superconducting Josephson element 201 and a capacitor 202 are connected in parallel.
• the superconducting Josephson element 201 consists of a pair of superconductors that exhibit superconductivity at a temperature below a predetermined critical temperature and an ultra-thin insulator with a thickness of several nanometers sandwiched between the pair of superconductors.
• the superconductor may for example be aluminum and the insulator may for example be aluminum oxide.
• each of the qubit elements 20 creates a quantum entanglement state with other adjacent qubit elements 20 to perform quantum operations.
• the resonator 21 reads a bit signal indicating the state of the qubit element 20 by interacting with the qubit element 20 .
• the resonator 21 is connected to the qubit element 20 via a capacitor (not shown).
• FIG. 4 is a diagram showing an example of the circuit configuration of the resonator 21. As shown in FIG.
• the resonator 21 includes a resonance circuit in which a superconducting inductor 211 and a capacitor 212 are connected in parallel.
• the readout electrode 22 is an electrode that is connected to the resonator 21 and for extracting the bit signal read out by the resonator 21 to the outside.
• FIG. 5 is a schematic cross-sectional view showing an example of the configuration of the quantum arithmetic device 10.
• the quantum arithmetic device 10 has a first substrate 30 and a second substrate 40 which are laminated.
• a qubit element 20 and a resonator 21 are provided on the first surface S1 of the first substrate 30 .
• the first substrate 30 is provided with through vias 31A and 31B.
• the through vias 31A and 31B each include a through hole 32 passing through the first substrate 30 and a conductive film 33 covering the inner wall of the through hole 32 .
• the conductive film 33 has portions extending to the first surface S1 of the first substrate 30 and the second surface S2 opposite to the first surface S1.
• the through via 31A is used to supply ground potential to the first substrate 30 and the second substrate 40 .
• the through via 31B functions as the readout electrode 22 .
• An insulator or a semiconductor can be used as the base material of the first substrate 30, and silicon, for example, can be preferably used.
• a conductive film 34 forming pads 25 and other wiring is provided on the surface of the first substrate 30 .
• the resonator 21 may be configured including this conductive film 34 .
• the pad 25 is electrically connected to the through via 31A, and is supplied with a ground potential from the outside through the through via 31A.
• the conductive films 33 forming the through vias 31A and 31B and the conductive films 34 forming the pads 25 and other wirings are preferably made of metal that exhibits superconductivity at a temperature equal to or lower than a predetermined temperature.
• TiN titanium nitride
• Al aluminum
• aluminum aluminum
• the second substrate 40 is laminated on the first surface S1 side of the first substrate 30 .
• the second substrate 40 functions as a cover that covers the qubit element 20 and the resonator 21 .
• the second substrate 40 has a cavity 41 on the surface facing the first surface S ⁇ b>1 of the first substrate 30 , and a space is formed around the qubit element 20 and the resonator 21 .
• the second substrate 40 has a plurality of bumps 42 provided on the outer periphery of the cavity 41 , and these bumps 42 are bonded to the pads 25 provided on the first substrate 30 . If a gap can be formed between the first substrate 30 and the second substrate 40, the cavity 41 may not be provided in the second substrate 40.
• FIG. 6A is a plan view showing an example of the configuration of the second substrate 40.
• FIG. 6B is a cross-sectional view along 6B-6B in FIG. 6A.
• a plurality of bumps 42 are arranged in a plurality of rows so as to surround cavity 41 .
• Each of the plurality of bumps 42 includes a plurality of convex portions 44 formed by the base material 43 of the second substrate 40, and conductive films 45A and 45B covering the surfaces of the plurality of convex portions 44. It is configured.
• the convex portion 44 is formed by finely processing the base material 43 by etching.
• the convex portion 44 has a cross-sectional area that intersects the stacking direction of the first substrate 30 and the second substrate 40 (that is, the height direction of the bump 42 ) and gradually decreases toward the tip of the bump 42 . That is, the convex portion 44 has a tapered shape.
• the convex portion 44 is a portion that becomes the core of the bump 42 .
• the conductive film 45 ⁇ /b>A covers the entire surface of the second substrate 40 facing the first substrate 30 , including the surfaces of the protrusions 44 .
• the conductive film 45B covers the surface of the conductive film 45A in the regions where the projections 44 of the second substrate 40 are formed.
• a portion of the conductive film 45A and the conductive film 45B covering the convex portion 44 constitutes the bump 42 .
• the conductive film 45A and the conductive film 45B have a tapered shape reflecting the shape of the convex portion 44 in the portion covering the convex portion 44 .
• the tip of the bump 42 protrudes from the surface of the base material 43, and when the second substrate 40 is superimposed on the first substrate 30 in the process of bonding the second substrate 40 to the first substrate 30, The tips of the bumps 42 are brought into contact with the first substrate 30 .
• the conductive film 45A and the conductive film 45B are each preferably made of a metal that exhibits superconductivity at a temperature below a predetermined temperature.
• TiN titanium nitride
• In indium
• An insulator or a semiconductor can be used as the base material 43 of the second substrate 40, and for example silicon can be preferably used. If the base material 43 is made of silicon, for example, the protrusions 44 forming the cores of the bumps 42 are made of silicon.
• FIG. 7 is a perspective view showing an example of the structure of the bump 42.
• the plurality of bumps 42 may have a conical shape. That is, the convex portion 44 formed on the base material 43 of the second substrate 40 can include a plurality of conical structure portions.
• the plurality of bumps 42 may have a pyramidal shape such as a triangular pyramid or square pyramid.
• the base material 43 of the second substrate 40 has a plurality of recesses 46 provided around each of the protrusions 44 .
• a plurality of recesses 46 are provided corresponding to each of the plurality of protrusions 44 .
• Each recess 46 surrounds the corresponding protrusion 44 .
• each of the protrusions 44 is provided inside the corresponding recess 46 .
• the recesses 46 are formed by etching regions corresponding to the periphery of the projections 44 of the base material 43 of the second substrate 40 .
• the convex portion 44 corresponds to a portion of the base material 43 that is left unetched in the etching for forming the concave portion 46 .
• FIG. 8A and 8B are cross-sectional views showing an example of a bonding method between the bumps 42 provided on the second substrate 40 and the pads 25 provided on the first substrate 30.
• FIG. 8A the tip of bump 42 (conductive film 45B) is bonded to pad 25 .
• a pressing force load
• the pressure shown in FIG. 8B is obtained.
• the tip of the bump 42 that is, the conductive film 45B is deformed so as to be crushed, and the bump 42 and the pad 25 are pressure-bonded. Bonding between the bumps 42 and the pads 25 is preferably performed at room temperature.
• a ground potential is supplied to the conductive film 45A covering the surface of the second substrate 40 by bonding the bumps 42 to the pads 25 .
• FIG. 9 is a diagram modeling the cone-shaped bump 42 .
• the radius of the bottom surface of the bump 42 is r
• the height of the bump 42 is h.
• ⁇ be the stress acting on the bump 42 when the pressing force F is applied to the bump 42
• d be the collapse amount of the bump 42
• S be the cross-sectional area of the collapsed tip of the bump 42 .
• the stress ⁇ can be expressed by the following equation (1)
• the pressing force F can be expressed by the following equation (2).
• ⁇ F/S (1)
• F ⁇ (dr/h) 2 (2)
• FIG. 10 is a graph showing an example of the relationship between the pressing force F applied to the bump 42 and the height h of the bump 42 when the bump 42 is deformed so that the crush amount d of the bump 42 is 0 to 10 ⁇ m. is.
• the initial height of the bump 42 is 15 ⁇ m
• the radius r of the bottom surface of the bump 42 is 5 ⁇ m
• the stress ⁇ is 2.14 MPa.
• the cross-sectional area S increases as the deformation of the bump 42 progresses, the pressing force F required to deform the bump 42 increases.
• the bumps 42 have a tapered shape, the area of the tips of the bumps 42 can be reduced. As a result, the bumps 42 can be deformed with a large crushing amount even with a relatively small pressing force. By increasing the amount of crushing of the bumps 42 , it is possible to apply a pressing force (load) to all the bumps 42 even when the heights of the bumps 42 become uneven due to manufacturing variations. That is, it is possible to reduce the risk of defective bonding occurring in some of the relatively low bumps.
• a method for manufacturing the quantum arithmetic device 10 will be described below. First, an example of a method for manufacturing the second substrate 40 will be described with reference to FIGS. 11A to 11H.
• a base material 43 of the second substrate 40 is prepared.
• a silicon substrate having a thickness of about 525 ⁇ m can be suitably used as the base material 43 (FIG. 11A).
• a resist 80 having a thickness of about 5 ⁇ m is formed on the surface of the base material 43 .
• the resist 80 is patterned corresponding to the bumps 42 by exposing and developing the resist 80 (FIG. 11B).
• a circular mask 80a having a diameter of ⁇ 1 is formed in a portion corresponding to the convex portion 44, and an annular opening 200b having a diameter of ⁇ 2 corresponding to the concave portion 46 is formed so as to surround the mask 80a.
• the diameter ⁇ 1 is, for example, about 15 ⁇ m, and the diameter ⁇ 2 is, for example, about 30 ⁇ m.
• a distance L1 between the openings 80b adjacent to each other is, for example, 25 ⁇ m.
• the inner peripheral portion of the surface of the base material 43 is covered with a mask 80c.
• the substrate 43 is etched using an ICP (Inductively Coupled Plasma) etching device (FIG. 11C). It is preferable to set the ICP power to 2000 W or less, the RF bias power to 35 W or less, the chamber pressure to 60 mTorr or less, and the gas ratio (C4F8:SF6) to 3:7.
• ICP Inductively Coupled Plasma
• the portions of the base material 43 exposed from the openings 80 b of the resist 80 are etched to form a plurality of annular concave portions 46 and the convex portions 44 are formed inside the concave portions 46 .
• the convex portion 44 is a portion of the base material 43 that remains without being etched.
• the diameter ⁇ 3 at the upper end of the concave portion 46 becomes larger than the diameter ⁇ 4 at the lower end. That is, a tapered concave portion 46 is formed.
• the convex portion 44 has a conical shape.
• the diameter ⁇ 3 at the upper end of the recess 46 is approximately 40 ⁇ m, and the diameter ⁇ 4 at the lower end of the recess 46 is approximately 30 ⁇ m.
• the depth D1 of the recess 46 is approximately 15 ⁇ m.
• the diameter ⁇ 5 at the lower end of the projection 44 is approximately 10 ⁇ m.
• a dry film 81 is formed on the surface of the base material 43 . Subsequently, the dry film 81 is exposed and developed to form openings 81a corresponding to the cavities 41 in the dry film 81 (FIG. 11D).
• a cavity 41 having a depth of about 300 ⁇ m is formed in the substrate 43 (FIG. 11E).
• Etching of the base material 43 can be performed by RIE (Reactive Ion Etching).
• RIE Reactive Ion Etching
• a step of covering the side surface of the cavity 41 in the process of being formed with a protective film and a step of further etching the bottom surface of the cavity 41 in the process of being formed are alternately performed.
• etching of the side surface of the cavity 41 is suppressed during etching of the bottom surface of the cavity 41 .
• CF gas is used in the step of covering the side surface of the cavity 41 with the protective film
• SF6 gas is used in the step of etching the bottom surface of the cavity 41 .
• a conductive film 45A with a thickness of about 0.2 ⁇ m is formed on the entire surface of the base material 43 by sputtering (FIG. 11F).
• TiN titanium nitride
• FIG. 11F a conductive film 45A with a thickness of about 0.2 ⁇ m is formed on the entire surface of the base material 43 by sputtering.
• TiN titanium nitride
• a dry film 82 is formed on the surface of the base material 43 . Subsequently, the dry film 82 is exposed and developed to form openings 82a corresponding to the bumps 42 in the dry film 82 (FIG. 11G).
• the opening 82a has a circular shape with a diameter of about 30 ⁇ m and is formed at the position where the bump 42 is formed.
• a conductive film 45B having a thickness of about 25 ⁇ m is formed on the exposed portion of the opening 82a of the dry film 82 on the surface of the conductive film 45A by vapor deposition (FIG. 11G).
• the conductive film 45B is also formed on the dry film 82.
• In (indium) can be suitably used as the material of the conductive film 45B.
• the conductive films 45 ⁇ /b>A and 45 ⁇ /b>B are formed along the surface shape of the base material 43 , and are formed in a conical shape reflecting the shape of the convex portion 44 in the portion covering the convex portion 44 .
• a conical bump 42 is formed on the second substrate 40 by laminating a convex portion 44, a conductive film 45A and a conductive film 45B.
• dry film 82 is removed together with conductive film 45B deposited on its surface (FIG. 11H). The second substrate 40 is completed through the above steps.
• a base material 35 of the first substrate 30 is prepared.
• a silicon substrate having a thickness of about 525 ⁇ m can be suitably used as the base material 35 (FIG. 12A).
• the heat dissipation substrate 90 is attached to the second surface S2 of the base material 35 .
• a resist 83 is formed on the first surface S1 of the base material 35, and openings 83a corresponding to the through vias 31A and 31B are formed in the resist 83 (FIG. 12B).
• the portion of the substrate 35 exposed from the opening 83a of the resist 83 is etched to form the through hole 32 in the substrate 35 (FIG. 12C).
• the heat generated during etching is diffused by the heat dissipation substrate 90, so that the temperature of the base material 35 is prevented from rising excessively.
• a conductive film 34 is formed on the entire first surface S1 and second surface S2 of the base material 35 by sputtering (FIG. 12D).
• TiN titanium nitride
• FIG. 12D a conductive film 34 is formed on the entire first surface S1 and second surface S2 of the base material 35 by sputtering.
• TiN titanium nitride
• a conductive film 33 is formed on the entire first surface S1 and second surface S2 of the substrate 35 by vapor deposition.
• the previously formed conductive film 34 is covered with the conductive film 33 .
• the conductive film 33 is also formed on the inner walls of the through holes 32 (FIG. 12E).
• Al (aluminum) can be suitably used as the material of the conductive film 33 .
• the conductive film 33 and the conductive film 34 are patterned by photolithography and etching. Through vias 31A and 31B, resonators 21, pads 25 and other wirings are thereby formed (FIG. 12F).
• the superconducting Josephson element that constitutes the qubit element 20 is formed by, for example, a step of forming a first electrode (not shown) containing Al (aluminum) on the first surface S1 of the base material 35 by vapor deposition, an O 2 gas
• a second electrode (not shown) containing Al (aluminum) is formed on the surface of the oxide film by a vapor deposition method. It is formed by going through the process of forming the
• the patterning of the first electrode and the second electrode may be performed, for example, by a lift-off method using a patterned resist (not shown).
• the opening pattern of the resist is a cross shape including a first linear portion along a first direction and a second linear portion along a second direction orthogonal to the first direction
• the first electrode may be formed in the portion corresponding to the first linear portion by performing the vapor deposition while tilting the first direction as the rotation axis.
• the second electrode may be formed in the portion corresponding to the second linear portion by performing the vapor deposition while tilting the rotation axis in the second direction. According to the above method, it is possible to pattern the first electrode and the second electrode with a single resist.
• the first substrate 30 is completed through the above steps.
• the first substrate 30 and the second substrate 40 are housed in a vacuum chamber (not shown), and the bonding surfaces of the first substrate 30 and the second substrate 40 are irradiated with an ion beam in the vacuum chamber (Fig. 13A).
• an ion beam in the vacuum chamber (Fig. 13A).
• elements that hinder bonding such as oxide films, hydroxyl groups, and water molecules present on the surfaces of the pads 25 and bumps 42 forming the bonding portions are removed, and the surfaces of the conductive films that constitute the pads 25 and bumps 42 are removed.
• An inert gas such as argon is used for the ion beam.
• the first substrate 30 and the second substrate 40 are bonded together in a vacuum chamber. That is, the second substrate 40 and the first substrate 30 are pressed against each other while the bumps 42 provided on the second substrate 40 and the pads 25 provided on the first substrate 30 are in contact with each other. Apply pressure (load). As a result, the tip of the bump 42 (the conductive film 45B) is deformed so as to be crushed, and the bump 42 and the pad 25 are joined. Bonding between the bumps 42 and the pads 25 is preferably performed at room temperature. Since the surfaces of the conductive films forming the bumps 42 and the pads 25 are activated by ion beam irradiation, it is possible to obtain firm bonding at room temperature (about 25° C.). This technique is called surface activation room temperature bonding. By performing the bonding between the substrates at room temperature, the characteristic fluctuation due to the heating of the quantum bit element 20 is suppressed. The quantum arithmetic device 10 is completed through the above steps.
• the quantum arithmetic device 10 includes the first substrate 30 provided with the circuit elements such as the qubit element 20 and the resonator 21, and the first substrate 30 laminated on the qubit. and a second substrate 40 covering the element 20 and the resonator 21 .
• the second substrate 40 is composed of a base material 43, and covers a tapered convex portion 44 whose cross-sectional area intersecting the stacking direction of the substrate gradually decreases toward the tip, and the surface of the convex portion 44. , a tapered conductive film 45A reflecting the shape of the convex portion 44; 45B and 45B.
• Bumps 42 are bonded to pads 25 of first substrate 30 .
• FIGS. 14A and 14B are cross-sectional views showing bonding between bumps 42X and pads 25X according to a comparative example.
• the area of the cross section intersecting the height direction is larger than that of the bump 42 in the first embodiment, and the height of the bump is generally constant. That is, the shape of the bump 42X is not tapered. Also, the height of the bumps 42X is uneven due to manufacturing variations.
• a pressing force is applied while the bumps 42X and the pads 25X are in contact with each other.
• the amount of crushing of the bump 42X with respect to a predetermined pressing force is small.
• the pressing force is not applied to some of the bumps 42X that are relatively low, and some of the bumps 42X that are relatively low are defective in bonding. may occur.
• the bumps 42 included in the quantum arithmetic device 10 according to the embodiment of the disclosed technology have a tapered shape, the area of the tips of the bumps 42 can be reduced. As a result, even with a relatively small pressing force, the bumps 42 can be deformed with a large crushing amount. By increasing the amount of crushing of the bumps 42, it is possible to apply a pressing force to all the bumps 42 even when the heights of the bumps 42 become uneven due to manufacturing variations. That is, it is possible to reduce the risk of defective bonding occurring in some of the relatively low bumps.
• FIG. 15 is a cross-sectional view showing an example of a method of forming the bump 42Y according to the comparative example.
• the bump 42Y according to the comparative example does not include the convex portion 44 according to the embodiment of the technology disclosed. That is, the bump 42Y does not have a core portion formed of the base material 43, but is formed only of the conductive film 45B.
• a bump 42Y according to the comparative example is formed by a lift-off method using a resist 200 having an opening 200a with a high aspect ratio. That is, the conductive film 45B forming the bump 42Y is deposited on the conductive film 45A exposed in the opening 200a of the resist 200. Then, as shown in FIG. However, according to this method, the minute openings 200a are blocked by the conductive film 45B before the bumps of sufficient height are formed. As a result, it becomes difficult to form bumps with a high aspect ratio.
• the bump 42 according to the embodiment of the disclosed technique covers the tapered convex portion 44 formed by the base material 43 of the second substrate 40 and the surface of the convex portion 44 so that the shape of the convex portion 44 is reflected. tapered conductive films 45A and 45B.
• the core portion of the bump 42 according to the embodiment of the disclosed technique is configured by the base material 43 .
• the base material 43 can be relatively easily microfabricated into a desired shape by an existing etching technique. By configuring the core portion of the bump 42 with the base material 43 of the second substrate 40, it is possible to easily form the fine bump 42 having a tapered shape and a high aspect ratio.
• the convex portion 44 can function as a stopper that prevents the bump 42 from being crushed excessively. Further, since the concave portion 46 is provided around the convex portion 44, the strength of the bump 42 can be ensured.
• FIG. 16A is a plan view showing an example of the configuration of the second substrate 40 according to the second embodiment of technology disclosed.
• FIG. 16B is a cross-sectional view along 16B-16B in FIG. 16A.
• a second substrate 40 according to the second embodiment differs from the first embodiment in the structure of bumps 42 .
• the convex portion 44 formed by the base material 43 of the second substrate 40 according to this embodiment has an integral annular structure surrounding the cavity 41 . That is, the substrate 43 of the second substrate 40 is provided with a convex portion 44 having a continuous rectangular crown shape surrounding the outer periphery of the circuit elements such as the qubit element 20 and the resonator 21 provided on the first substrate 30.
• the convex portion 44 has a tapered shape in which the cross-sectional area intersecting the height direction gradually decreases toward the tip.
• the shape of the portion of the convex portion 44 that forms one side of the crown-like structure may be a quadrangular pyramid.
• the second substrate 40 has recesses 46 provided around the protrusions 44 .
• the concave portion 46 is provided in a crown shape along the crown-like structure of the convex portion 44 .
• the quantum arithmetic device it is possible to suppress poor bonding of bumps, as with the quantum arithmetic device 10 according to the first embodiment.
• the bumps 42 have an integral annular structure, the space around the qubit element 20 and the resonator 21 can be sealed. By evacuating this space, adsorption of substances to the qubit element 20 can be suppressed without forming a protective film that causes dielectric loss on the surface of the qubit element 20 .
• FIG. 17 is a cross-sectional view showing an example of the configuration of a quantum arithmetic device 10A according to the third embodiment of technology disclosed.
• the quantum arithmetic device 10A according to the third embodiment is characterized in that the first substrate 30 is provided with the bumps 36 that constitute the bonding portion between the first substrate 30 and the second substrate 40. 2 differs from the quantum arithmetic device 10 according to the second embodiment.
• the bump 36 is composed of the base material 35 of the first substrate 30, and has a tapered shape in which the cross-sectional area intersecting the stacking direction of the first substrate 30 and the second substrate 40 gradually decreases toward the tip. includes a convex portion 38 of .
• the bump 36 includes tapered conductive films 34 and 37 that cover the surface of the projection 38 and reflect the shape of the projection 38 . According to the quantum arithmetic device 10A according to the third embodiment, like the quantum arithmetic device 10 according to the first embodiment, it is possible to suppress bonding defects of bumps.
• the disclosed technique is not limited to this aspect.
• the technology disclosed herein can be applied to electronic devices including circuit elements other than superconducting devices, such as transistors, resistive elements, and capacitors.
• Quantum arithmetic device 10 Quantum bit element 10 Quantum bit element 30 First substrate 35 Base material 40 Second substrate 36, 42, 42X, 42Y Bump 43 Base material 44 Projections 34, 37, 45A, 45B Conductive film

Landscapes

• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Computational Mathematics (AREA)
• Pure & Applied Mathematics (AREA)
• Data Mining & Analysis (AREA)
• Evolutionary Computation (AREA)
• Artificial Intelligence (AREA)
• Mathematical Analysis (AREA)
• Mathematical Optimization (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Computing Systems (AREA)
• General Engineering & Computer Science (AREA)
• Mathematical Physics (AREA)
• Software Systems (AREA)
• Manufacturing & Machinery (AREA)
• Wire Bonding (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Priority Applications (4)

Applications Claiming Priority (1)

Related Child Applications (1)

Publications (1)

Family

ID=87564009

Family Applications (1)

Country Status (4)

Cited By (1)

Citations (9)

• 2022
  • 2022-02-14 WO PCT/JP2022/005649 patent/WO2023152961A1/ja not_active Ceased
  • 2022-02-14 JP JP2023580031A patent/JP7750315B2/ja active Active
  • 2022-02-14 EP EP22925980.9A patent/EP4482284A4/en active Pending
• 2024
  • 2024-07-25 US US18/784,252 patent/US20240389478A1/en active Pending

Patent Citations (9)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events