JP7454530B2 - 金属部品 - Google Patents
金属部品 Download PDFInfo
- Publication number
- JP7454530B2 JP7454530B2 JP2021123496A JP2021123496A JP7454530B2 JP 7454530 B2 JP7454530 B2 JP 7454530B2 JP 2021123496 A JP2021123496 A JP 2021123496A JP 2021123496 A JP2021123496 A JP 2021123496A JP 7454530 B2 JP7454530 B2 JP 7454530B2
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- Prior art keywords
- plating layer
- lead frame
- shear strength
- base material
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/60—Electroplating characterised by the structure or texture of the layers
- C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/46—Electroplating: Baths therefor from solutions of silver
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
最初に、図1を参照しながら、実施形態に係るリードフレーム1および半導体装置100について説明する。図1の(a)は、実施形態に係るリードフレーム1の模式図であり、図1の(b)は、実施形態に係る半導体装置100を示す断面図である。
つづいて、実施形態に係るリードフレーム1の詳細について、図2を参照しながら説明する。図2は、実施形態に係るリードフレーム1の拡大断面図である。
[実施例1]
最初に、銅を主成分とするリードフレームの基材を準備した。次に、基材の脱脂及び酸洗浄を行った後、電解めっき処理によって、基材の表面に、電解めっき処理でAgめっき層を形成した。
上述の実施例1と同様な方法を用いて、表面に凹凸形状が形成されたAgめっき層を有する実施例2~14のリードフレームを得た。なお、実施例2~14では、Agめっき層に形成される凸部のアスペクト比がさまざまな値となるように、電解めっき処理の条件を適宜調整した。
最初に、銅を主成分とするリードフレームの基材を準備した。次に、基材の脱脂及び酸洗浄を行った。これにより、比較例1のリードフレームを得た。すなわち、比較例1のリードフレームは、表面にAgめっき層が形成されず、銅の基材がそのまま露出するリードフレームである。
最初に、銅を主成分とするリードフレームの基材を準備した。次に、基材の脱脂及び酸洗浄を行った後、電解めっき処理によって、基材の表面に、電解めっき処理でAgめっき層を形成した。
[比較例3]
最初に、銅を主成分とするリードフレームの基材を準備した。次に、基材の脱脂及び酸洗浄を行った後、電解めっき処理によって、基材の表面に、電解めっき処理でAgめっき層を形成した。
次に、測定温度が変化した場合のシア強度の推移(すなわち、リードフレームに加わる熱履歴が変化した場合のシア強度の推移)について評価した。具体的には、図3に示した樹脂カップが表面に形成された実施例1のリードフレームに対して、160(℃)~400(℃)の間の所定の温度で10分間保持した後のシア強度をそれぞれ測定した。結果を図10に示す。
次に、実施例1および比較例2のリードフレームを用いて半導体装置を組み立てた際の組立評価と、実施例1および比較例2のリードフレームを用いて組み立てられた半導体装置の信頼性評価とを実施した。結果を表1に示す。
2 基材
2a 表面
3 めっき層(貴金属めっき層の一例)
3a 表面
3b 凸部
100 半導体装置
101 半導体素子
102 ボンディングワイヤ
103 封止樹脂
Claims (4)
- 半導体装置の製造に用いられる金属部品において、
導電性を有する基材と、
前記基材の表面の全面または一部に形成される貴金属めっき層と、
を備え、
前記貴金属めっき層は、表面に凹凸形状を有し、前記凹凸形状における凸部のアスペクト比が0.3以上であり、
前記貴金属めっき層を封止樹脂で封止し、260(℃)に加熱した際の前記貴金属めっき層と前記封止樹脂との間のシア強度が、1.7(MPa)以上である
金属部品。 - 半導体装置の製造に用いられる金属部品において、
導電性を有する基材と、
前記基材の表面の全面または一部に形成される貴金属めっき層と、
を備え、
前記貴金属めっき層は、表面に凹凸形状を有し、前記凹凸形状における凸部のアスペクト比が0.3以上であり、
前記貴金属めっき層を封止樹脂で封止し、260(℃)に加熱した際の前記貴金属めっき層と前記封止樹脂との間のシア強度が、加熱前の前記貴金属めっき層と前記封止樹脂との間のシア強度の10(%)以上である
金属部品。 - 前記貴金属めっき層は、Agを主成分として含有する
請求項1または2に記載の金属部品。 - 前記凸部のアスペクト比が0.5以上である
請求項1~3のいずれか一つに記載の金属部品。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2021123496A JP7454530B2 (ja) | 2021-07-28 | 2021-07-28 | 金属部品 |
CN202210824388.1A CN115692353A (zh) | 2021-07-28 | 2022-07-14 | 金属部件 |
EP22185760.0A EP4124678A1 (en) | 2021-07-28 | 2022-07-19 | Metal component |
US17/871,281 US20230047332A1 (en) | 2021-07-28 | 2022-07-22 | Metal component |
JP2023202508A JP7696979B2 (ja) | 2021-07-28 | 2023-11-30 | 金属部品 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2021123496A JP7454530B2 (ja) | 2021-07-28 | 2021-07-28 | 金属部品 |
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JP2023202508A Division JP7696979B2 (ja) | 2021-07-28 | 2023-11-30 | 金属部品 |
Publications (2)
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JP2023019035A JP2023019035A (ja) | 2023-02-09 |
JP7454530B2 true JP7454530B2 (ja) | 2024-03-22 |
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JP2021123496A Active JP7454530B2 (ja) | 2021-07-28 | 2021-07-28 | 金属部品 |
JP2023202508A Active JP7696979B2 (ja) | 2021-07-28 | 2023-11-30 | 金属部品 |
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JP2023202508A Active JP7696979B2 (ja) | 2021-07-28 | 2023-11-30 | 金属部品 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20230047332A1 (ja) |
EP (1) | EP4124678A1 (ja) |
JP (2) | JP7454530B2 (ja) |
CN (1) | CN115692353A (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2024101669A (ja) * | 2023-01-18 | 2024-07-30 | 株式会社三井ハイテック | 金属部品 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020155746A (ja) | 2019-03-22 | 2020-09-24 | 大口マテリアル株式会社 | リードフレーム |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH053277A (ja) | 1991-06-25 | 1993-01-08 | Hitachi Ltd | 半導体装置 |
JPH0786484A (ja) * | 1993-09-14 | 1995-03-31 | Matsushita Electron Corp | 樹脂封止型半導体装置 |
US6720642B1 (en) * | 1999-12-16 | 2004-04-13 | Fairchild Semiconductor Corporation | Flip chip in leaded molded package and method of manufacture thereof |
JP3841768B2 (ja) * | 2003-05-22 | 2006-11-01 | 新光電気工業株式会社 | パッケージ部品及び半導体パッケージ |
JP4887533B2 (ja) * | 2006-09-29 | 2012-02-29 | Dowaメタルテック株式会社 | 銀めっき金属部材およびその製造法 |
US20160204003A1 (en) * | 2015-01-08 | 2016-07-14 | Yiu Fai KWAN | Method of forming asper-silver on a lead frame |
JP6650723B2 (ja) * | 2015-10-16 | 2020-02-19 | 新光電気工業株式会社 | リードフレーム及びその製造方法、半導体装置 |
JP6733941B1 (ja) * | 2019-03-22 | 2020-08-05 | 大口マテリアル株式会社 | 半導体素子搭載用基板 |
US11629426B1 (en) * | 2022-06-29 | 2023-04-18 | Rohm And Haas Electronic Materials Llc | Silver electroplating compositions and methods for electroplating rough matt silver |
-
2021
- 2021-07-28 JP JP2021123496A patent/JP7454530B2/ja active Active
-
2022
- 2022-07-14 CN CN202210824388.1A patent/CN115692353A/zh active Pending
- 2022-07-19 EP EP22185760.0A patent/EP4124678A1/en active Pending
- 2022-07-22 US US17/871,281 patent/US20230047332A1/en active Pending
-
2023
- 2023-11-30 JP JP2023202508A patent/JP7696979B2/ja active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020155746A (ja) | 2019-03-22 | 2020-09-24 | 大口マテリアル株式会社 | リードフレーム |
Also Published As
Publication number | Publication date |
---|---|
US20230047332A1 (en) | 2023-02-16 |
CN115692353A (zh) | 2023-02-03 |
EP4124678A1 (en) | 2023-02-01 |
JP2023019035A (ja) | 2023-02-09 |
JP2024024647A (ja) | 2024-02-22 |
JP7696979B2 (ja) | 2025-06-23 |
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