541362 玖、發明說明 本發明是有關於一種無鉛電鍍製程，且特別是有關 於一種以無鉛電鍍方式形成含有錫的鍍層，且避免產生鬚 晶的製程。 電鍍製程（plating)是廣泛應用於諸多電子產品的製 程，包括半導體封裝中承載器（carrier)製作中的電鍍，或 者印刷電路板（PCB)製作中的電鍍。比如：導線架（leadframe) 的表面經常使用電鍍，以改善其接合性（bondability)，封 裝性（moldability)及焊接性（solderability)，或者印刷電路 板的接點上鍍錫鉛合金，防止銅的氧化，並利於後續的焊 接。其中，焊接金屬的電鍍是經常使用的製程，其可以改 善焊接時的接合性，並提高焊點的可靠度，而錫鉛合金即 是最常見的焊接金屬（solder)鐽層材料。然而，由於世界各 國的環保意識抬頭，對於電鍍產業造成極大的衝擊，尤其 是含重金屬鉛的錫鉛電鍍製程首當其衝，未來重金屬高污 染的電鍍製程將受到嚴格管制。因此，無鉛的電子產品將 是未來的產品趨勢，而取代錫鉛合金的焊接金屬材料包 括·錫祕合金、錫銅合金、錫銀合金及純錫寺’並採用無 鉛的電鍍製程。 然而，習知無鈴電鍍（lead free plating)的製程常有 錫鬚的產生，而造成不預期的短路現象，其主要原因在於 鍍層間的內應力使得錫在電鍍過程中朝一特定方向生長， 形成錫鬚。雖然在電鍍液中添加少量特定比例的非錫金 屬，可以抑制錫鬚的生長，然而無鉛電鍍製程中對鍍層少 6736tvvfl.doc/008 5 |_錫成分之控制仍不穩定，故至今仍無法完全避免錫鬚 的產生。 因此本發明的目的之一就是在提供一種無鉛電鍍製 程’以形成一無鉛且含錫的鍍層。 本發明的另一目的在於提出一種無鉛電鍍製程，用 以避免錫鬚的產生，提高電鍍電子產品的良率。 爲達成本發明之上述和其他目的，提出一種無鉛電 _製程，其步驟包括：提供一基材並在基材表面閃鍍一層 。接著進行一無鉛電鍍製程，形成一含有錫的鍍層。 依照本發明的一較佳實施例，其中基材包括材質爲 _或銅合金的導線架；含有錫的鍍層材質包括錫鉍合金、 锡銅合金、錫銀合金或純錫。至於閃鍍純銅的電鍍液包括： 硫酸銅、焦磷酸銅及氫氧化銅的混合液。對於電鍍錫鉍合 金’其電鍍液含有甲基磺酸、錫離子及鉍離子；電鍍純錫’ 則其電鍍液含有甲基磺酸及錫離子；而電鍍錫銅合金，其 電鍍液則含有甲基磺酸、錫離子及銅離子。 錯由無給電鍍前，先在基材表面閃鑛一層純銅’ 可以提供一較柔軟的表面，可以降低或釋放鍍層間的內應 力，使得後續的無鉛電鍍製程避免錫鬚的產生。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖式’作 詳細說明如下： 圖式之簡單說明： 第1圖繪示習知以導線架爲承載器的封裝製程。 6736twfl .doc/008 6 541362 第2圖繪示依照本發明第一較佳實施例的一種半導 體封裝應用無鉛電鍍的流程圖。 第3圖繪示對應第2圖之半導體封裝的部分剖面 圖。 第4圖繪示依照本發明第二較佳實施例的一種半導 體封裝應用無鉛電鍍的流程圖。 第5圖繪示對應第4圖之半導體封裝的部分剖面 圖。 第6圖繪示本發明無鉛電鍍製程的特徵流程圖。 表一列舉本發明進行實驗的各種半導體封裝產品， 及其導線架之底材。 表二列舉本發明中各含有錫的鍍層之無鉛電鍍條 件。 圖式之標示說明： 10、20、30、40、50、60 :步驟 100、102、104、106、108、110、112 :步驟 300、302、304、306、308、310、312 :步驟 400、402、404 :步驟 200 :導線架 202 :晶片座 204 :導腳 206 :內導腳部分 208 :外導腳部分 210、214 :純銅層 6736twfl .doc/008 7 2 12 :含有錫的鍍層 220 :晶片 222 :黏著材料 224 :導線 226 :焊墊 228 :封裝材料 MMlMl 壯制:瞻照第1目’其繪示習知以導線架爲承載器的封 衣次彳壬。以〜般導線架的焊接金屬電鍍爲例，一般導線架 ，半導體对裝係先提供一導線架（如步驟10所示），然後進 行曰曰片貼附步驟（die attaching)，如步驟2〇所示，將晶片 垃過一黏著材料（adhesive)貼附於導線架的晶片座（die pad) 或者導腳（lead)上。接著，進行打導線步驟（wire bonding)， 如步驟30所示，以導線，比如金線或鋁線，分別將晶片 之焊墊與對應之導腳電性連接。然後，進行封膠步驟 (encapsulating)，如步驟4〇所示，以封裝材料（腦1土叫 compound)包覆晶片、晶片座、導腳之內導腳部分（inner丨⑽ portion)，及連接晶片與導腳的導線，並暴露出導腳之外 導腳部分、(outer lead portion)。接著電鍍焊接金屬（s〇lde〇 於外導腳部分，如步驟50所示。最後，如步驟6〇所示， 將封裝之半導體封裝單元自導線架上切離（trinming)，並 將外導腳折Μ成型（f〇rming)，以形成所需的導腳型態，比 如 J 型（J-lead)，海鷗型（guii_wing lead)等。 就導線架焊接金屬電鍍的應用而言，本發明即是要 6736tvvfl .doc/008 8 541362 改善第1圖中步驟50的電鍍方式，採用無給電鑛，並避 免錫鬚的產生。 又 ^ 本發明選用多種半導體封裝產品進行實驗，靑多^照 表一，其列舉本發明進行實驗的各種半導體封裝產品，及 其導線架之底材。包括：1·腳位數24的塑膠型雙排Z封裝 (PDIP 24L)，其導線架底材係採用編號〇LI]sU94的銅材衣 2.腳位數1〇〇的四方扁平封裝（QFP 100L)，其導，線架底材 係採用編號OLIN7025的銅材。3.腳位數44的塑勝刑無接 腳晶粒封裝（PLCC 4礼）’其導線架底材係^采^^編^ OLINIM的銅材。4·腳位數28的薄小型封裝（EI 2Sl)，其 導線架底材係採用編號Alloy 42的銅合金。這幽封裝分別 對應現行各種常用的封裝結構’及不同的導腳間^〇ead pitch) 〇 請同時參照第2圖及第3圖，其中第2圖繪示依照 本發明第一較佳實施例的一種半導體封裝應用無給電鑛的 流程圖’第3圖繪示對應第2圖之半導體封裝的部分剖面 圖。如步驟100所示，本發明導線架型半導體封裝係=提 供一導線架2〇〇，然後在導線架的表面先閃鍍（flash p^ting) 一層純銅、21〇，如步驟102所示。進行晶片貼附步驟，如 步驟1〇4所不，將晶片22〇透過一黏著材料222貼附於導 線架2〇〇的晶片座2〇2上。接著，進行打導線步驟，如步 驟106所示，以導線224，比如金線或鋁線，分別將晶片 220之知墊226與對應之導腳2〇4電性連接。然後，進行 封膠步驟，如步驟108所示，以封裝材料2M包覆晶片72〇、 6736twfl.doc/008 9 541362 晶片座202、導腳204之內導腳部分2〇6，及連接晶片22〇 與導腳204的導線224，並暴露出導腳204之外導腳部分 2〇8°接者以無錯電鍍〜含有錫的鍍層212於外導腳部分 208，如步驟110所示。最後，如步驟112所示，將封裝 之半導體封裝單元自導線架上切離，並將外導腳2〇8折彎 成型，以形成所需的導腳型態，比如〗型，海鷗型等。 由於在無鉛電鍍前先在導線架2〇〇表面閃鍍一層純 銅210 ’其材質較爲柔軟，可以有效降低或釋放鍍層間的 內應力，以避免錫鬚的生成。 此外，本發明的流程上尙有另一種選擇，請同時參 照第4圖及第5圖，料第4 _雜照本㈣第二較佳 =施麵-種半導體封裝應用無鈴電鍍的流程圖，第5圖 糸曾二封應弟4圖之半導體封裝_分剖面圖。如步驟· 所不、，本發明雜架’導體賴縣提供—_架2〇〇， 然後進行晶片貼附步驟，如步驟3〇2所示，將晶片22〇透 過一站者材料222貼附於導線架2〇〇的晶片座2〇2上。接 著’進行打導線步驟，如步驟3〇4所示，以導線224，比 如金線或銘線，分別將晶片220之焊墊226與對應之導腳 2〇4電性連接。然後，進行封膠步驟，如步驟3〇6所示， 以封裝材料228包覆晶片220、晶片座202、導腳204之 內導腳邰分206，及連接晶片220與導腳204的導線224， 並暴露出導腳204之外導腳部分208。接著閃鍍一層純銅 214 h外導腳邰分208，如步驟所示；然後以無給電 鍍一含有錫的鍍層212於純銅2M表面，如步驟3 1〇所示。 6736twfl.doc/0〇8 541362 最後，如步驟312所示，將封裝之半導體封裝單元自導線 架上切離，並將外導腳208折彎成型，以形成所需的導腳 型態，比如J型，海鷗型等。 同樣地，在外導腳部分208表面由於在無鉛電鍍前 先在導線架200表面閃鍍一層純銅214,其材質較爲柔軟， 可以有效降低或釋放鍍層間的內應力，以避免錫鬚的生 成。 上述二實施例中，閃鍍純銅層的步驟所採用的電鍍 液包括硫酸銅、焦磷酸銅及氫氧化銅的混合溶液。而關於 無鉛電鍍的電鍍條件請參照表二，其列舉本發明中各含有 錫的鍍層之無鉛電鍍條件。舉例而言= 1. 若含有錫的鍍層之材質爲純錫，其電鍍液則含有 甲基磺酸及錫離子。其中甲基磺酸的濃度約爲100〜200 克/公升（較佳爲150克/公升），錫離子濃度約50〜100克/ 公升（較佳爲70克/公升），電鍍溫度約20〜60度C(較佳爲 40度C)，另外可以添加體積分率約6%的添加物，用以調 整電鍍速率及使鍍層表面明亮。 2. 若含有錫的鍍層之材質爲錫鉍合金，其電鍍液則 含有甲基磺酸、錫離子及鉍離子。其中甲基磺酸的濃度約 100〜200克/公升（較佳爲140克/公升），錫離子的濃度約 30〜70克/公升（較佳爲55克/公升），鉍離子的濃度約1〜 5克/公升（較佳爲2克/公升），其電鍍溫度約20〜60度C(較 佳爲40度C)，另外可以添加體積分率約40ml/LT的添加 物，用以調整電鍍速率及使鍍層表面明亮。 6736twfl.doc/008 541362 3.若含有錫的鑛層之材質爲錫銅合金，其電鍍液則 含有甲基磺酸、錫離子及銅離子。其中甲基磺酸的濃度約 100〜2〇〇克/公升（較佳爲11〇克/公升），錫離子的濃度約 5〇〜100克/公升（較佳爲7〇克/公升），銅離子的濃度約 〜2克/公升（$父佳爲0.5克/公升），其電鍍溫度約2〇〜⑽ 度C($父佳爲40度C)，另外可以添加體積分率約6%的添 加物，用以調整電鍍速率及使鍍層表面明亮。 w 以上述之電鍍條件針對表〜之各種半導體封裝之導 線架進行電鑛’並以對照組方式進行實驗，即一組導線架 未進行純銅之閃鍍，而另一組則在無鉛電鍍前進行純銅= 閃鍍。貫驗結果發現：未進行純銅閃鍍之導線架會產生錫 鬚；而藉由本發明的製程，在無鉛電鍍前進行純銅閃鍍， 確實可以防止錫鬚的產生。 雖然前述二實施例係以電子產品中半導體封裝導線 架之電鍍爲例，然而對於其他產品在進行含有錫鍍層的無 鉛電鍍時，均可以運用本發明無鉛電鍍製程以改善錫鬚所 衍生的問題。請參照第6圖，其繪示本發明無鉛電鍍製程 的特徵流程圖。根據本發明對於含錫鍍層的無鉛電鍍，如 圖所示係在提供一基材後（如步驟400所示），於基材上閃 鍍一純銅或以銅在基材表面打底（如步驟4〇2所示）。其中 基材包括導線架、印刷電路板、封裝基板，或者半導體封 裝的接點等。接著，再進行含有錫的鍍層之無鉛電鍍，^ 於純銅鍍層的柔軟特性，使得無鉛電鍍時可以避免錫鬚的 產生，減低短路現象的發生，提高產品良率。 6736twfl .doc/008 541362 綜上所述，本發明提出的無鉛電鍍製程，可以符合 未來環保的需求，提供低污染的電鍍製程。並且，可以形 成品質較佳的含錫鍍層，避免錫鬚的產生，免除不必要的 短路現象，提高產品品質。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 6736twfl.doc/008541362 (ii) Description of the invention The present invention relates to a lead-free electroplating process, and more particularly to a process for forming a tin-containing plating layer by using a lead-free electroplating method and avoiding the generation of whiskers. The plating process is a process widely used in many electronic products, including plating in the manufacture of carriers in semiconductor packages, or plating in the manufacture of printed circuit boards (PCBs). For example, the surface of the leadframe is often electroplated to improve its bondability, moldability and solderability, or tin-lead alloy plating on the contacts of the printed circuit board to prevent copper Oxidation and facilitate subsequent welding. Among them, electroplating of welding metal is a frequently used process, which can improve the jointability during welding and improve the reliability of solder joints, and tin-lead alloy is the most common solder layer material. However, due to the rise of environmental awareness in various countries around the world, it has caused a great impact on the electroplating industry, especially the tin-lead electroplating process containing heavy metal lead. The plating process of heavy metals with high pollution will be strictly controlled in the future. Therefore, lead-free electronic products will be the product trend of the future. Welding metal materials including tin-lead alloys include tin alloys, tin-copper alloys, tin-silver alloys, and pure tin temples, and lead-free plating processes are used. However, in the conventional process of lead free plating, tin whiskers are often generated, which leads to unexpected short circuits. The main reason is that the internal stress between the plating layers causes the tin to grow in a specific direction during the plating process. Tin whisker. Although the addition of a small amount of non-tin metal in the plating solution can suppress the growth of tin whiskers, the lead-free plating process has less plating 6673tvvfl.doc / 008 5 | _ tin composition is still unstable, so it is still not complete Avoid tin whiskers. It is therefore an object of the present invention to provide a lead-free plating process' to form a lead-free and tin-containing plating layer. Another object of the present invention is to provide a lead-free electroplating process to avoid the generation of tin whiskers and improve the yield of electroplated electronic products. In order to achieve the above and other objectives of the present invention, a lead-free electrical process is proposed. The steps include: providing a substrate and flash-plating a layer on the surface of the substrate. Next, a lead-free electroplating process is performed to form a plating layer containing tin. According to a preferred embodiment of the present invention, the substrate includes a lead frame made of _ or a copper alloy; and the tin-containing coating material includes tin-bismuth alloy, tin-copper alloy, tin-silver alloy, or pure tin. As for the electroplating solution of flash-plated pure copper, a mixed solution of copper sulfate, copper pyrophosphate and copper hydroxide. For electroplated tin-bismuth alloys, the electroplating solution contains methanesulfonic acid, tin ions, and bismuth ions; for electroplated pure tin, the electroplating solution contains methanesulfonic acid and tin ions; and for electroplated tin-copper alloys, the electroplating solution contains formazan. Sulfonic acid, tin ion and copper ion. Before the electroless plating, a layer of pure copper is flashed on the surface of the substrate, which can provide a softer surface, which can reduce or release the internal stress between the plating layers, so that the subsequent lead-free electroplating process can avoid the generation of tin whiskers. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings' as follows: Brief description of the drawings: Figure 1 Illustrate a conventional packaging process using a lead frame as a carrier. 6736twfl .doc / 008 6 541362 FIG. 2 shows a flow chart of applying lead-free plating to a semiconductor package according to the first preferred embodiment of the present invention. FIG. 3 is a partial cross-sectional view of the semiconductor package corresponding to FIG. 2. FIG. 4 is a flowchart illustrating a semiconductor package applying lead-free plating according to a second preferred embodiment of the present invention. FIG. 5 is a partial cross-sectional view of the semiconductor package corresponding to FIG. 4. FIG. 6 shows a characteristic flowchart of the lead-free plating process of the present invention. Table 1 lists the various semiconductor packaging products and the substrates of the lead frames that are tested in the present invention. Table 2 lists the lead-free plating conditions of each tin-containing plating layer in the present invention. Description of the drawings: 10, 20, 30, 40, 50, 60: steps 100, 102, 104, 106, 108, 110, 112: steps 300, 302, 304, 306, 308, 310, 312: step 400 , 402, 404: Step 200: Lead frame 202: Chip holder 204: Guide pin 206: Inner guide pin portion 208: Outer guide pin portion 210, 214: Pure copper layer 6736twfl.doc / 008 7 2 12: Tin-containing plating layer 220 : Wafer 222: Adhesive material 224: Wire 226: Welding pad 228: Packaging material MMlMl Zhuang: Look at the first item 'its drawing shows the conventional coating sub-units using the lead frame as a carrier. Take the welding metal plating of a lead frame as an example. For a general lead frame, the semiconductor mounting system first provides a lead frame (as shown in step 10), and then performs a die attaching step, as in step 2. As shown, the wafer is pasted with an adhesive material on a die pad or a lead of a lead frame. Next, a wire bonding step is performed. As shown in step 30, the pads of the chip are electrically connected to corresponding lead pins by wires, such as gold wires or aluminum wires, respectively. Then, an encapsulating step (encapsulating) is performed. As shown in step 40, the chip, the chip holder, the inner guide portion of the guide pin, and the connection are covered with an encapsulation material (compound called brain compound). The chip and the lead wires are exposed, and the outer lead portions outside the lead pins are exposed. Next, a solder metal is plated (s0lde〇 on the outer lead portion, as shown in step 50. Finally, as shown in step 60, the packaged semiconductor package unit is trimmed from the lead frame, and the outer lead is trimmed. Folding is formed to form the required guide pin shape, such as J-lead, guii_wing lead, etc. As far as the application of leadframe welding metal plating is concerned, the present invention That is, 6736tvvfl.doc / 008 8 541362 is used to improve the electroplating method in step 50 in the first figure, using no-power ore and avoiding the generation of tin whiskers. Also, the present invention selects a variety of semiconductor packaging products for experiments. First, it enumerates various semiconductor packaging products and substrates for lead frames of the present invention. It includes: 1 · Plastic double-row Z package (PDIP 24L) with 24 pin numbers. The lead frame substrates are numbered. 〇LI] sU94's copper clothing 2. Quad flat package (QFP 100L) with 100 feet, its guide, the wire frame substrate is made of copper with the number OLIN7025. 3. Plastic victory with 44 feet Pinless die package (PLCC 4th) 'The lead frame substrate system ^ mining ^^ ^ OLINIM copper. 4. Thin and small package (EI 2Sl) with 28 pin positions. The lead frame substrate is made of copper alloy No. 42. This package corresponds to the current commonly used packaging structures. Between the guide feet ^ 〇ead pitch) 〇 Please refer to FIG. 2 and FIG. 3 at the same time, wherein FIG. 2 shows a flowchart of a semiconductor package application without power ore according to the first preferred embodiment of the present invention. A partial cross-sectional view of the semiconductor package corresponding to FIG. 2 is shown. As shown in step 100, the leadframe-type semiconductor packaging system of the present invention is provided with a leadframe 200, and then the surface of the leadframe is first flash-plated with a layer of pure copper 21o, as shown in step 102. The wafer attaching step is performed. As in step 104, the wafer 22 is attached to the wafer holder 200 of the lead frame 200 through an adhesive material 222. Next, as shown in step 106, a conducting wire step is performed, and the conducting pad 226 of the chip 220 and the corresponding guide pin 204 are electrically connected with a conducting wire 224, such as a gold wire or an aluminum wire, respectively. Then, a sealing step is performed. As shown in step 108, the wafer 72 is covered with the packaging material 2M, 6736twfl.doc / 008 9 541362 wafer holder 202, the inner guide pin portion 204 of the guide pin 204, and the connection chip 22 〇The wire 224 with the guide pin 204 exposes the guide pin portion 208 outside the guide pin 204. The connection is plated without error ~ a plating layer 212 containing tin is formed on the outer guide pin portion 208, as shown in step 110. Finally, as shown in step 112, the packaged semiconductor package unit is cut off from the lead frame, and the outer guide pin 208 is bent to form a desired guide pin shape, such as a square shape, a seagull shape, etc. . Since a layer of pure copper 210 'is flash-plated on the leadframe 200 surface before lead-free plating, its material is relatively soft, which can effectively reduce or release the internal stress between the plating layers to avoid the formation of tin whiskers. In addition, there is another option in the process of the present invention. Please refer to FIG. 4 and FIG. 5 at the same time. , Figure 5: Zeng Erfeng Yingdi 4 semiconductor package _ sectional view. As shown in the steps, the present invention provides the hybrid rack 'conductor Lai County—200 racks, and then the wafer attaching step is performed, as shown in step 302, the wafer 22 is passed through the one-stop material 222 and attached. On the wafer holder 200 of the lead frame 200. Next, a conducting wire step is performed. As shown in step 304, the bonding pad 226 of the chip 220 and the corresponding lead pin 204 are electrically connected with a conducting wire 224, such as a gold wire or a name wire, respectively. Then, a sealing step is performed. As shown in step 306, the encapsulation material 228 is used to cover the chip 220, the chip holder 202, the lead pin 206 inside the guide pin 204, and the wire 224 connecting the chip 220 and the guide pin 204. , And the guide leg portion 208 outside the guide leg 204 is exposed. Then flash-plating a layer of pure copper 214h outer guide pin 208, as shown in the steps; then, a plating layer 212 containing tin is electrolessly plated on the surface of pure copper 2M, as shown in step 310. 6736twfl.doc / 0〇8 541362 Finally, as shown in step 312, cut off the packaged semiconductor packaging unit from the lead frame, and bend the outer guide pin 208 to form the required lead pin shape, such as J type, seagull type, etc. Similarly, on the surface of the outer guide pin portion 208, a layer of pure copper 214 is flash-plated on the surface of the lead frame 200 before lead-free plating. The material is relatively soft, which can effectively reduce or release the internal stress between the plating layers to avoid the formation of tin whiskers. In the above two embodiments, the plating solution used in the step of flash-plating the pure copper layer includes a mixed solution of copper sulfate, copper pyrophosphate and copper hydroxide. Regarding the plating conditions for lead-free plating, please refer to Table 2, which lists the lead-free plating conditions of each tin-containing plating layer in the present invention. For example = 1. If the material of the tin-containing coating is pure tin, the plating solution contains methanesulfonic acid and tin ions. The concentration of methanesulfonic acid is about 100 ~ 200 g / L (preferably 150 g / L), the concentration of tin ion is about 50 ~ 100 g / L (preferably 70 g / L), and the plating temperature is about 20 ~ 60 ° C (preferably 40 ° C). In addition, an additive with a volume fraction of about 6% can be added to adjust the plating rate and make the surface of the coating bright. 2. If the tin-containing coating is made of tin-bismuth alloy, the plating solution contains methanesulfonic acid, tin ions, and bismuth ions. The concentration of methanesulfonic acid is about 100 to 200 g / liter (preferably 140 g / liter), the concentration of tin ions is about 30 to 70 g / liter (preferably 55 g / liter), and the concentration of bismuth ion is about 1 ~ 5g / liter (preferably 2g / liter), its plating temperature is about 20 ~ 60 ° C (preferably 40 ° C), and an additive with a volume fraction of about 40ml / LT can be added for Adjust the plating rate and make the plating surface bright. 6736twfl.doc / 008 541362 3. If the material of the tin-containing ore layer is a tin-copper alloy, the plating solution contains methanesulfonic acid, tin ions, and copper ions. The concentration of methanesulfonic acid is about 100 ~ 200 g / liter (preferably 110 g / liter), and the concentration of tin ion is about 50 ~ 100 g / liter (preferably 70 g / liter), The concentration of copper ions is about ~ 2 g / liter ($ father's good is 0.5 grams / liter), and its plating temperature is about 20 ~ ⑽ ° C ($ father's good is 40 degrees C), and the volume fraction can be added about 6% Additives are used to adjust the plating rate and make the coating surface bright. w Use the above electroplating conditions for the leadframes of the various semiconductor packages listed in Table ~ and perform experiments in a control group, that is, one set of leadframes is not flash-plated with pure copper, and the other set is subjected to lead-free plating. Pure copper = flash plating. The results of the inspection found that the lead frame without pure copper flash plating would produce tin whiskers; and through the process of the present invention, pure copper flash plating before lead-free plating could indeed prevent the generation of tin whiskers. Although the foregoing two embodiments take the electroplating of semiconductor package leadframes in electronic products as an example, when other products are used for lead-free electroplating with a tin plating layer, the lead-free electroplating process of the present invention can be used to improve the problems caused by tin whiskers. Please refer to FIG. 6, which shows a characteristic flowchart of the lead-free plating process of the present invention. For the lead-free electroplating of the tin-containing coating according to the present invention, as shown in the figure, after a substrate is provided (as shown in step 400), a pure copper is flash-plated on the substrate or the substrate is primed with copper (as shown in step) 4〇2). The substrate includes lead frames, printed circuit boards, package substrates, or semiconductor package contacts. Next, the lead-free plating of the tin-containing plating layer is performed, and the soft characteristics of the pure copper plating layer make it possible to avoid the occurrence of tin whiskers during lead-free plating, reduce the occurrence of short circuits, and improve product yield. 6736twfl .doc / 008 541362 In summary, the lead-free electroplating process proposed by the present invention can meet the needs of future environmental protection and provide a low pollution electroplating process. In addition, a better quality tin-containing coating can be formed, avoiding the generation of tin whiskers, eliminating unnecessary short circuits, and improving product quality. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 6736twfl.doc / 008
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0LIN194 0LIN7025 0LIN151 Alloy42 應用ms PDIP24L QFP100L PLCC44L EI28L 541362 表0LIN194 0LIN7025 0LIN151 Alloy42 Application ms PDIP24L QFP100L PLCC44L EI28L 541362 table
Pure Sn(觀） Sn-Bi_ Sn-Cu(^^) Sn2+:70g/LT Sn2+:55g/LT Sn2+:70g/LT na Bi3+:2.0g/LT Cu:0.5g/LT 甲繊:150gAT 甲顯:140g/LT 甲繊:110g/LT mm：e%y/y _:40ml/LT 添脑:6%v/v m：4〇°c m-A〇°c m：wcPure Sn (View) Sn-Bi_ Sn-Cu (^^) Sn2 +: 70g / LT Sn2 +: 55g / LT Sn2 +: 70g / LT na Bi3 +: 2.0g / LT Cu: 0.5g / LT Formazan: 150gAT 140g / LT Formazan: 110g / LT mm: e% y / y _: 40ml / LT Brain: 6% v / vm: 4 ° c mA mA °°: wc