JPS59149042A - Lead frame for semiconductor - Google Patents
Lead frame for semiconductorInfo
- Publication number
- JPS59149042A JPS59149042A JP2341883A JP2341883A JPS59149042A JP S59149042 A JPS59149042 A JP S59149042A JP 2341883 A JP2341883 A JP 2341883A JP 2341883 A JP2341883 A JP 2341883A JP S59149042 A JPS59149042 A JP S59149042A
- Authority
- JP
- Japan
- Prior art keywords
- tin
- lead frame
- semiconductor
- solder
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はトランジスタ等の半導体装置の組立に用いら
れる半導体用リードフレームに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor lead frame used for assembling semiconductor devices such as transistors.
電子機器、特に半導体装置の組立に用いられるリードフ
レームについては、グイボンディング。Gui bonding is used for lead frames used in the assembly of electronic equipment, especially semiconductor devices.
ワイヤゼンデイング等の組立性を満足させるだめ各種の
合金から成る導体の表面にニッケル捷たはニッケル合金
めっきを施し、さらにその上にＡｕまだはＡｇめつきを
施すことが広く行なわれていた。In order to satisfy the ease of assembly such as wire wrapping, it has been widely practiced to apply nickel strip or nickel alloy plating to the surface of a conductor made of various alloys, and to further apply Au or Ag plating thereon.
しかしながら、ＡｇまだはＡｌｌめっきは貴金属であり
高価であるから、半導体装置のコストに占める割合が高
いという欠点がある。そこで、’Ａ、ｕ”ｌたはＡｇめ
つきの厚さを薄くしたり、めっきを部分的に行なったり
して安価な半導体を製造、提供する努力も払われている
。これらの名前金属化からさらに進んで、貴金属を用い
ずに半導体装置を組立てる技術として、例えばＡｕ線を
用いるワイヤゼンデイングの代りにｋｔのワイヤ昶ンデ
ィングを用いることも行なわれている。However, since Ag and Al plating are precious metals and are expensive, they have the disadvantage that they account for a high proportion of the cost of the semiconductor device. Therefore, efforts are being made to manufacture and provide inexpensive semiconductors by reducing the thickness of 'A, u''l or Ag plating or by performing plating partially.These names are based on metallization. Further, as a technique for assembling semiconductor devices without using noble metals, for example, KT wire winding is being used instead of wire winding using Au wire.
一方、半導体素子をリードフレームにろう接するグイ昶
ンデイングにおいてはＡｕ −Ｓｉ共晶接合を行なうの
が一般的であったが、最近ではそれに代えてりＩン状の
半田箔やＡｇペーストを使用する傾向にある。しかしな
がら、Ａｕ−８ｉ共共晶台法と比較すると ＩＪ 、）
？ン状の半田箔を用いる場合には箔供給装置が必要とな
る他、フラックスの使用による問題、Ａｇペーストを用
いる場合の含有成分の問題など半導体装置の信頼性を損
う問題が生じている。On the other hand, when soldering a semiconductor element to a lead frame, it was common to use Au-Si eutectic bonding, but recently, in-line solder foil or Ag paste has been used instead. There is a tendency. However, when compared with the Au-8i eutectic platform method, IJ,)
? When using solder foil in the form of a solder, a foil supplying device is required, and there are also problems that impair the reliability of the semiconductor device, such as problems caused by the use of flux and problems with the components contained when using Ag paste.
さらに、一般に外部リード部には半田付は性を向上させ
るために樹脂による封止後に半田溶融めっき法或いは電
気めっき法による錫まだは半田めっきが行なわれている
が、このような外部リード部へのめつきにはフラックス
を用いたり酸洗したりする前処理が必要であり、酸の残
存が半導体装置の信頼性を低下させる一つの要因となっ
ている。Furthermore, in order to improve the soldering properties of external leads, solder plating is generally performed on the external leads using hot-dip solder plating or electroplating after sealing with resin. Plating requires pretreatment such as using flux or pickling, and residual acid is one of the factors that reduces the reliability of semiconductor devices.
唸た、外部ＩＪ ）％へのめっき自体も半導体装置の
コストアップの要因の一つである。However, external IJ plating itself is one of the factors that increases the cost of semiconductor devices.
この発明の目的は、上述した従来技術の欠点を解消し、
貴金属を全く使用せず１信頼性の高い、かつ安価な半導
体装置を構成することのできるリードフレームを提供す
ることにある。The purpose of this invention is to solve the above-mentioned drawbacks of the prior art,
An object of the present invention is to provide a lead frame capable of constructing a highly reliable and inexpensive semiconductor device without using any precious metals.
この発明は、半導体素子をダイボンディングする素子配
置部と１半導体装置の組立後に電子部品として糺込んだ
とき良好な半田付性が要求される外部ＩＪ −ｐ部とに
錫まだは半田（錫−鉛合金）めつき層を設けたことを特
徴とする。すなわち、半導体用リードフレームの全面に
錫まだは半田めっき層を設けたり、ＡＩ−或いはＡｕ線
に」：リワイヤツＳンデイングするインナーソー１部に
錫丑たは半田めっきを設けたりすると、ワイヤボンディ
ング性が失われて全く接続できない事態が生じる。しだ
がって、少なくともワイヤボンデイングされるインカー
リ−１５部には錫壕だは半田めっき層は不要であり、こ
の発明では上記のように素子配置部および外部り−１部
のみに錫まだは半田めっき層が設けられている。This invention provides an element placement section for die-bonding semiconductor devices and an external IJ-p section that requires good solderability when bonded as an electronic component after assembling a semiconductor device. It is characterized by having a plating layer (lead alloy). In other words, if a tin or solder plating layer is provided on the entire surface of a semiconductor lead frame, or if a tin or solder plating is provided on the first part of the inner saw that is to be rewired for AI or Au wires, the wire bonding properties will be improved. A situation arises where the connection is lost and no connection is possible. Therefore, there is no need for a tin groove or a solder plating layer on at least the 15 portions of the incurry to be wire bonded, and in the present invention, as described above, tin or solder is not required only on the element placement portion and the outer portion. A plating layer is provided.
以、下、図面を参照してこの発明の一実施例について説
明する。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図はリン青銅から成る基体１を打抜き成形したリー
ドフレームの平面図であり、２は半導体素子配置部（ダ
イボンド部）、３はインナーリード部（ワイヤボン１部
）を示す。FIG. 1 is a plan view of a lead frame formed by punching and forming a base body 1 made of phosphor bronze, with reference numeral 2 indicating a semiconductor element placement portion (die bonding portion), and numeral 3 indicating an inner lead portion (wire bond 1 portion).
第２図はリードフレームの断面図であり、該ジ−１３フ
レームの全面には光沢ニッケルめっき層４が２μ、壕だ
Ｐ −Ｎ ｉ合金めつき層５が０５μの厚さでそれぞれ
設けられ、さらにダイボンド部２と外部リード部６には
錫捷だは半田めっき層７が設けられている。すなわち、
前記り−Ｐフレームを脱脂、酸洗等により前処理した後
、ワット浴中で光沢ニッケルめっき（電気めっき、光沢
剤は上利工業■製の「アサヒライト」を使う）を２μの
厚さで行ない、さらに電気Ｐ−Ｎｉめっき浴中でＰ−Ｎ
ｉ合金めつきを厚さ０５μで行ない、このリードフレー
ムを用いて図示するようにダイボンド部２と外部リード
部６とにホウフッ化錫めっき浴により電気錫めっきを０
．５μの厚さで行なうことにより構成したものである。FIG. 2 is a cross-sectional view of the lead frame, and the entire surface of the G-13 frame is provided with a bright nickel plating layer 4 with a thickness of 2 μm and a grooved P-Ni alloy plating layer 5 with a thickness of 05 μm. Further, the die bonding portion 2 and the external lead portion 6 are provided with a solder plating layer 7 made of tin. That is,
After pre-treating the above-mentioned P frame by degreasing, pickling, etc., it was coated with bright nickel plating (electroplating, using "Asahi Light" manufactured by Kamiri Kogyo ■ as the brightener) in a Watts bath to a thickness of 2μ. P-Ni plating in an electric P-Ni plating bath.
I-alloy plating is performed to a thickness of 05 μm, and using this lead frame, electrolytic tin plating is applied to the die bond portion 2 and external lead portion 6 using a tin borofluoride plating bath as shown in the figure.
．． It is constructed by forming the film with a thickness of 5 μm.
第３図はこの発明のリードフレームを用いて組立てた半
導体装置を示す。すなわち、１ず半導体素子であるシリ
コンベレット８を４０００の温度で錫めっき層７にダイ
ボンディングし、次いでシリコンベレット８とインナー
リード部３とをＡｕ１だは、ａのワイヤ９でワイヤボン
ディングした後、樹脂１０で樹脂モールＰで封止して保
護することにより構成したものである。このような工程
を経て ５−
も外部＋） Ｉ：′部７の錫めっき層は要求される半
田付性を十分満足するものとなっている。FIG. 3 shows a semiconductor device assembled using the lead frame of the present invention. That is, first, the silicon pellet 8, which is a semiconductor element, is die-bonded to the tin plating layer 7 at a temperature of 4,000 °C, and then the silicon pellet 8 and the inner lead part 3 are wire-bonded with a wire 9 of Au1 or A. It is constructed by sealing and protecting the resin 10 with a resin molding P. Through such a process, the tin plating layer on the outside +) I:' portion 7 satisfies the required solderability.
第４図は打抜き前のリードフレームに予め錫または半田
めっき層を形成した後、＋） ＦＳフレームを打抜き
成形した場合の例を示しだものである。FIG. 4 shows an example in which a tin or solder plating layer is formed on a lead frame before punching, and then a +) FS frame is punched and formed.
なお、ダイボンド部２と外部リード部６に設けられる錫
まだは半田めっき層は同一の組成もしくは厚さにする必
要はなく、適宜変えることができる。The tin and solder plating layers provided on the die bonding part 2 and the external lead part 6 do not need to have the same composition or thickness, and can be changed as appropriate.
また、錫まだは半田めっき層には必要に応じて微量の第
２もしくは第３元素、例えばＳｂ、Ｚｎ、Ｉｎ。In addition, if necessary, a trace amount of a second or third element such as Sb, Zn, or In may be added to the solder plating layer.
ｃｄ、 Ａｇ、 Ａｕ 、 Ｂｉ 、 Ｏｕ等を含有さ
せることもできる。It can also contain cd, Ag, Au, Bi, Ou, etc.
以上、この発明の実施例および態様について説明したが
、この発明によれば、（１） Ａｕ−８ｉ共晶などの高
価な金属を使用せずにダイボンディングを行なうので半
導体装置のコストが低下し、（２）半田箔などの供給装
置が不要となり作業性が向上し、（３）外部リ−１５に
予め半田付性の良好な錫または半田めっきを施している
ので後の工程が不要となる等、半導体装置の低価格化に
寄与することができ ６ −
る。The embodiments and aspects of the present invention have been described above. According to the present invention, (1) die bonding is performed without using expensive metals such as Au-8i eutectic, so the cost of semiconductor devices is reduced; , (2) Workability is improved as a supply device such as solder foil is not required, and (3) Since the external lead 15 is pre-plated with tin or solder which has good solderability, subsequent processes are not required. etc., it can contribute to lowering the cost of semiconductor devices.
第１図は打抜き成形した半導体用リードフレームの平面
図、第２図はこの発明の半導体用リードフレームの断面
図、第３図はこの発明の半導体用＋） ｈ％フレーム
を用いて組立てた半導体装置の平面図、第４図はこの発
明の別の態様を示す平面図および断面図である。
なお、図中、同一符号は同−捷たけ相当部分を示す。
ｌ・・・基体、２・・半導体素子配置部（グイボンド部
）、３・・・インナーリード部（ワイヤボンド部）、４
・・・ニッケルめっき、５・・・Ｐ−ＮＩめっき、６
・列部リード部、７・・・錫捷だは半田めっき部、８・
・・半導体素子（ンリコンペレソト）、９・・・Ａ／、
’７ ’ｆ ヤ、１０・・・樹脂。
代理人 弁理士 佐 藤 不二雄
７−
第１ 図 第１図
減３図
１８３Fig. 1 is a plan view of a punched and formed semiconductor lead frame, Fig. 2 is a sectional view of the semiconductor lead frame of the present invention, and Fig. 3 is a semiconductor assembled using the semiconductor lead frame of the present invention. A plan view of the device, FIG. 4 is a plan view and a sectional view showing another embodiment of the present invention. In the drawings, the same reference numerals indicate the same parts. l...Base body, 2...Semiconductor element placement part (gui bond part), 3...Inner lead part (wire bond part), 4
...Nickel plating, 5...P-NI plating, 6
・Row part lead part, 7...Solder plating part for tin plate, 8.
・・Semiconductor element (Nricomperesoto), 9...A/,
'7'f Ya, 10...resin. Agent Patent Attorney Fujio Sato 7- Figure 1 Figure 1 Reduced Figure 3 183
Claims (2)
部）２と外部リード部６とに錫または半田（錫−鉛合金
）めっき層７を設けて成る半導体用り−Ｐフレーム。(1) A P-frame for semiconductors, in which a tin or solder (tin-lead alloy) plating layer 7 is provided on the semiconductor element placement portion (die portion) 2 and the external lead portion 6 of the lead frame.
び（または）ニッケル合金めっき層５を設けた後に、そ
の半導体素子配置部（ダイプント部）２と外部リード部
６とに錫まだは半田（錫−鉛合金）めっき層７を設けて
成る特許請求の範囲（１）記載の半導体用リードフレー
ム。(2) After providing the nickel plating layer 4 and/or nickel alloy plating layer 5 on the entire surface of the lead frame, if there is no tin or solder (tin- A semiconductor lead frame according to claim (1), comprising a lead alloy (lead alloy) plating layer 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2341883A JPS59149042A (en) | 1983-02-15 | 1983-02-15 | Lead frame for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2341883A JPS59149042A (en) | 1983-02-15 | 1983-02-15 | Lead frame for semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59149042A true JPS59149042A (en) | 1984-08-25 |
Family
ID=12109947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2341883A Pending JPS59149042A (en) | 1983-02-15 | 1983-02-15 | Lead frame for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59149042A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5019893A (en) * | 1990-03-01 | 1991-05-28 | Motorola, Inc. | Single package, multiple, electrically isolated power semiconductor devices |
| EP0671763A2 (en) * | 1994-03-07 | 1995-09-13 | Texas Instruments Incorporated | Ultrasonically welded plastic support ring for handling and testing semiconductor devices |
| US6613451B1 (en) * | 1998-09-11 | 2003-09-02 | Nippon Mining & Metals Co., Ltd. | Metallic material |
| KR100861048B1 (en) | 2007-02-27 | 2008-09-30 | 쌍용자동차 주식회사 | Measuring system for headform impact portion and angle to indicator panel of vehicle |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5224467A (en) * | 1975-08-20 | 1977-02-23 | Sony Corp | Mounting method of electric element |
| JPS55108757A (en) * | 1979-02-15 | 1980-08-21 | Toshiba Corp | Semiconductor device |
| JPS5792854A (en) * | 1980-11-29 | 1982-06-09 | Toshiba Corp | Plastic molded type semiconductor device |
| JPS5793535A (en) * | 1980-12-03 | 1982-06-10 | Hitachi Ltd | Semiconductor device |
| JPS57145352A (en) * | 1981-03-04 | 1982-09-08 | Hitachi Cable Ltd | Lead frame for semiconductor |
-
1983
- 1983-02-15 JP JP2341883A patent/JPS59149042A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5224467A (en) * | 1975-08-20 | 1977-02-23 | Sony Corp | Mounting method of electric element |
| JPS55108757A (en) * | 1979-02-15 | 1980-08-21 | Toshiba Corp | Semiconductor device |
| JPS5792854A (en) * | 1980-11-29 | 1982-06-09 | Toshiba Corp | Plastic molded type semiconductor device |
| JPS5793535A (en) * | 1980-12-03 | 1982-06-10 | Hitachi Ltd | Semiconductor device |
| JPS57145352A (en) * | 1981-03-04 | 1982-09-08 | Hitachi Cable Ltd | Lead frame for semiconductor |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5019893A (en) * | 1990-03-01 | 1991-05-28 | Motorola, Inc. | Single package, multiple, electrically isolated power semiconductor devices |
| EP0671763A2 (en) * | 1994-03-07 | 1995-09-13 | Texas Instruments Incorporated | Ultrasonically welded plastic support ring for handling and testing semiconductor devices |
| EP0671763A3 (en) * | 1994-03-07 | 1997-04-09 | Texas Instruments Inc | Ultrasonically welded plastic support ring for handling and testing semiconductor devices. |
| US6613451B1 (en) * | 1998-09-11 | 2003-09-02 | Nippon Mining & Metals Co., Ltd. | Metallic material |
| KR100861048B1 (en) | 2007-02-27 | 2008-09-30 | 쌍용자동차 주식회사 | Measuring system for headform impact portion and angle to indicator panel of vehicle |
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