JPH05117898A - Lead frame for mounting semiconductor chip and production thereof - Google Patents

Lead frame for mounting semiconductor chip and production thereof

Info

Publication number
JPH05117898A
JPH05117898A JP3282608A JP28260891A JPH05117898A JP H05117898 A JPH05117898 A JP H05117898A JP 3282608 A JP3282608 A JP 3282608A JP 28260891 A JP28260891 A JP 28260891A JP H05117898 A JPH05117898 A JP H05117898A
Authority
JP
Japan
Prior art keywords
lead frame
layer
alloy
thickness
plating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3282608A
Other languages
Japanese (ja)
Other versions
JP2925815B2 (en
Inventor
Takafumi Morikawa
貴文 森川
Akitomo Shirakawa
亮偕 白川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP3282608A priority Critical patent/JP2925815B2/en
Publication of JPH05117898A publication Critical patent/JPH05117898A/en
Application granted granted Critical
Publication of JP2925815B2 publication Critical patent/JP2925815B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PURPOSE:To produce a lead frame excellent in wire bonding properties at a low cost by successively forming a primary coat of Zn and Sn, etc., an intermediate layer of Ni and the uppermost layer of Pd and Au, etc., on the lead frame main body. CONSTITUTION:A lead frame main body A is obtained by pressing Cu-Cr-Sn-Zn alloy and forming a pad part 1, inner leads 2, a dibber part 3 and outer leads 4, etc. This main body A is coated with Zn, Sn, Pb, In, Co, Cr or alloy thereof or alloy of these and Cu to form a primary coat having 0.01-0.2mum thickness. This primary coat is coated with an intermediate Ni layer having 0.05-2.0mum thickness. Furthermore this intermediate layer is coated with the uppermost layer of Pd, Au, Ag, Pt or alloy thereof having 0.01-0.2mum thickness. The coating is preferably performed by an electroplating method. Thereby the lead frame for mounting semiconductor chips is obtained which is excellent in wire bonding properties, solderability, adhesive properties of resin, corrosion resistance, adhesive properties of plating and bending properties.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体チップ実装用リー
ドフレームとその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting lead frame and its manufacturing method.

【0002】[0002]

【従来の技術】トランジスタ,ICなどの電子部品を実
装するために用いるリードフレームは、通常、図1の平
面図で示したような構造になっている。すなわち、全体
は金属製であり、半導体チップを搭載するパッド部1の
周囲に複数本のインナーリード2が前記パッド部1と離
隔して配置され、このインナーリード2はダイバー部3
を介してアウターリード4と連結されている。
2. Description of the Related Art A lead frame used for mounting electronic parts such as transistors and ICs usually has a structure as shown in the plan view of FIG. That is, the entirety is made of metal, and a plurality of inner leads 2 are arranged around the pad portion 1 on which the semiconductor chip is mounted so as to be spaced apart from the pad portion 1.
It is connected to the outer lead 4 via.

【0003】このリードフレームは、通常、Fe−Ni
合金やCu合金から成る板材にプレス加工やエッチング
加工を施して、図1で示した形状のリードフレーム本体
とし、ついで、パッド部1およびインナーリード2に
は、Agなどの貴金属を厚み3〜5μm程度スポットめ
っきして、その個所の酸化防止が図られたものである。
このリードフレームへの半導体チップの実装は、概ね、
次のようにして行われる。
This lead frame is usually made of Fe--Ni.
A plate material made of an alloy or Cu alloy is pressed or etched to form a lead frame main body having the shape shown in FIG. 1, and then a noble metal such as Ag is applied to the pad portion 1 and the inner lead 2 in a thickness of 3 to 5 μm. Spot plating is performed to some extent to prevent oxidation at that location.
Mounting of a semiconductor chip on this lead frame is generally
This is done as follows.

【0004】すなわち、図2で示したように、まず、パ
ッド部1の上に接着剤5を用いて半導体チップ6がダイ
ボンディングされる。ついで、この半導体チップ6に予
め装荷されている電極パッド7とインナーリード2と
を、Au,AlまたはCuから成るワイヤ8によってワ
イヤボンディングして電気的に接続する。その後、前記
ボンディングした個所の全体を例えばエポキシ樹脂のよ
うな封止樹脂9で封止する。
That is, as shown in FIG. 2, first, the semiconductor chip 6 is die-bonded onto the pad portion 1 using the adhesive 5. Then, the electrode pad 7 preloaded on the semiconductor chip 6 and the inner lead 2 are wire-bonded with a wire 8 made of Au, Al or Cu to electrically connect them. Then, the entire bonded portion is sealed with a sealing resin 9 such as an epoxy resin.

【0005】ついで、アウターリード4に例えばSn−
Pb合金めっきを施してその半田付け性を向上させたの
ち、ダイバー部3を切断し、バリ取りを行いアウターリ
ード4に曲げ加工を施す。このようにして製造された部
品は、プリンド配線基板に搭載され、その必要配線とア
ウターリード4とを半田付けして目的とする電子部品に
なる。
Then, for example, Sn-
After the Pb alloy plating is applied to improve the solderability, the diver portion 3 is cut, deburred, and the outer lead 4 is bent. The component manufactured in this manner is mounted on the printed wiring board, and the required wiring and the outer lead 4 are soldered to form a desired electronic component.

【0006】ところで、前記したアウターリード4への
めっき処理は、通常、溶融めっきまたは電気めっきを適
用して行われている。しかしながら、溶融めっきにおい
ては、その浴温度が240〜300℃と高温であるた
め、半導体チップ実装後の部品をめっき浴中に浸漬した
ときに、大きな熱衝撃を受けて封止樹脂とリードフレー
ム本体との間に微細な間隙が生ずるという問題がある。
By the way, the plating treatment on the outer leads 4 is usually performed by applying hot dipping or electroplating. However, in hot-dip plating, the bath temperature is as high as 240 to 300 ° C., so when the components after mounting the semiconductor chips are immersed in the plating bath, they are subjected to a large thermal shock and the sealing resin and the lead frame body are There is a problem that a minute gap is generated between

【0007】また、電気めっきの場合には、用いるめっ
き浴は一般にアルカリ性または酸性であるため、封止樹
脂が部分的に侵食されてめっき浴のイオンが封止樹脂中
に侵入し、その結果、ワイヤや電極パッドの腐食が引き
起こされることがある。このようなことから、溶融めっ
き、電気めっきのいずれの処理においても、得られた電
子部品はその信頼性が低下してしまうという問題が起こ
りやすい。
Further, in the case of electroplating, since the plating bath used is generally alkaline or acidic, the sealing resin is partially eroded and the ions of the plating bath penetrate into the sealing resin, resulting in Corrosion of wires and electrode pads may occur. For this reason, in both the hot dipping and electroplating processes, the reliability of the obtained electronic component is likely to deteriorate.

【0008】このため、最近では、アウターリードに予
めSn−Pb合金を電気めっきしておき、そのリードフ
レームに半導体チップを実装するという方法が行われて
いる。しかしながら、この方法の場合、後工程であるボ
ンディング時に、その熱によってめっきしたSn−Pb
合金が溶融したり、または、リードフレーム本体がCu
であったときには、めっき層であるSn−Pb合金とC
uとが相互拡散してSnとCuの化合物を生成し、その
結果、アウタリードの半田付け性が低下するという問題
を引き起こしている。
For this reason, recently, a method has been performed in which an outer lead is electroplated with a Sn--Pb alloy in advance and a semiconductor chip is mounted on the lead frame. However, in the case of this method, Sn-Pb plated by the heat at the time of bonding which is a later step is used.
Alloy melts or leadframe body is Cu
When it is, the Sn-Pb alloy and C which are plating layers
This causes a problem that u and interdiffuse to form a compound of Sn and Cu, and as a result, the solderability of the outer leads is deteriorated.

【0009】これらの問題を解決するために、アウター
リードにPdを電気めっきしたリードフレームが提案さ
れている(特開昭59−168659号公報,特開昭6
3−2358号公報,特開平2−42753号公報など
を参照)。Pdは大気中で安定であるため酸化しにく
く、またリードフレーム本体との熱拡散もほとんど起こ
さないので、上記リードフレームは、ワイヤとのボンデ
ィング性も良好で、半田付け性や樹脂との密着性も良好
となる。そのため、パッド部やインナーリードへのAg
のスポットめっきも不要となり、また、アウターリード
へSn−Pb合金などをめっきすることも不要になる。
In order to solve these problems, a lead frame in which outer leads are electroplated with Pd has been proposed (Japanese Patent Laid-Open Nos. 59-168659 and 6-59).
(See Japanese Patent Application Laid-Open No. 3-2358, Japanese Patent Application Laid-Open No. 2-42753, etc.). Since Pd is stable in the air, it is difficult to oxidize, and it hardly causes thermal diffusion with the lead frame body. Therefore, the lead frame has good wire bondability, solderability and resin adhesion. Is also good. Therefore, Ag on the pad and inner leads
Spot plating is also unnecessary, and it is also unnecessary to plate the outer lead with a Sn-Pb alloy or the like.

【0010】しかしながら、Pdは非常に高価である。
したがって、工業的な観点からいえば、リードフレーム
本体にめっきするPdの厚みはできるだけ薄くすること
が好ましい。そのために、最近では、リードフレーム本
体とPdめっき層との間に下地層としてNiめっき層を
介在させ、このNiめっき層でリードフレーム本体の腐
食防止を行わせることにより、Pdめっき層の厚みを薄
くするということが行われている。
However, Pd is very expensive.
Therefore, from the industrial point of view, it is preferable to make the thickness of Pd plated on the lead frame body as thin as possible. Therefore, recently, a Ni plating layer is interposed between the lead frame body and the Pd plating layer as an underlayer, and the Ni plating layer prevents corrosion of the lead frame body, thereby reducing the thickness of the Pd plating layer. It is being thinned.

【0011】[0011]

【発明が解決しようとする課題】ところで、Niめっき
層の場合、その厚みが2μm以上になると、曲げ加工を
行ったときに、その加工部分にクラックが顕著に発生す
る。このことは、アウターリードに曲げ加工を行うとき
の不都合な問題になる。したがって、Niめっき層を薄
くすれば上記不都合は解消できるわけであるが、しか
し、このNiめっき層の厚みが薄くなればなるほど、そ
のめっき層にはピンホールが多発するようになり、リー
ドフレーム本体の腐食を防止する機能が低下してしま
う。リードフレーム本体の腐食を完全に防止するために
は、このNiめっき層の厚みを5μm以上にすることが
必要である。
By the way, in the case of the Ni plating layer, when the thickness thereof is 2 μm or more, when the bending process is performed, cracks remarkably occur in the processed portion. This is an inconvenient problem when the outer lead is bent. Therefore, the above inconvenience can be solved by thinning the Ni plating layer. However, as the thickness of the Ni plating layer becomes thinner, pinholes frequently occur in the plating layer, and the lead frame body The function of preventing the corrosion of is deteriorated. In order to completely prevent the corrosion of the lead frame body, it is necessary that the thickness of the Ni plating layer be 5 μm or more.

【0012】このようなことから、単にNiめっき層を
介在させるだけでは、Pdめっき層の厚みが薄く、しか
も耐食性と曲げ加工性の両者の特性を備えたリードフレ
ームを得ることは極めて困難であった。本発明は、従来
のリードフレームにおける上記した問題を解決し、ワイ
ヤとの優れたボンディング性,良好な半田付け性や樹脂
密着性を備え、アウターリードの曲げ加工時にもクラッ
クがほんど発生しない半導体チップ実装用リードフレー
ムとその製造方法の提供を目的とする。
Therefore, it is extremely difficult to obtain a lead frame having a thin Pd plating layer and having both corrosion resistance and bending workability by simply interposing the Ni plating layer. It was The present invention solves the above-mentioned problems in conventional lead frames, has excellent bonding properties with wires, good solderability, and resin adhesion, and is a semiconductor in which cracks hardly occur during bending of outer leads. An object of the present invention is to provide a chip mounting lead frame and a manufacturing method thereof.

【0013】[0013]

【課題を解決するための手段】上記した問題を解決する
ために、本発明においては、リードフレーム本体と、前
記リードフレーム本体の上に形成されて成る、Zn,S
n,Pb,In,Co,Cdの群から選ばれる少なくと
も1種の金属もしくはそれらの合金または前記金属とC
uとの合金の下地層と、前記下地層の上に形成されて成
る、Niの中間層と、前記中間層の上に形成されて成
る、Pd,Au,Ag,Ptの群から選ばれる少なくと
も1種の金属またはそれらの合金の最上層とを備えてい
ることを特徴とする半導体チップ実装用リードフレーム
が提供され、また、リードフレーム本体の全面を、Z
n,Sn,Pb,In,Co,Cdの群から選ばれる少
なくとも1種の金属もしくはそれらの合金または前記金
属とCuとの合金で被覆して下地層を形成し、ついで、
前記下地層の表面をNiで被覆して中間層を形成し、最
後に、前記中間層の表面を、Pd,Au,Ag,Ptの
群から選ばれる少なくとも1種の金属またはそれらの合
金で被覆して最上層を形成することを特徴とする半導体
チップ実装用リードフレームの製造方法が提供される。
In order to solve the above problems, in the present invention, a lead frame body and Zn, S formed on the lead frame body are formed.
at least one metal selected from the group consisting of n, Pb, In, Co and Cd, an alloy thereof, or the above metal and C
At least one selected from the group consisting of an underlayer of an alloy of u, an intermediate layer of Ni formed on the underlayer, and an intermediate layer of Pd, Au, Ag, Pt formed on the intermediate layer. Provided is a lead frame for mounting a semiconductor chip, which is provided with a top layer of one kind of metal or an alloy thereof, and the entire surface of the lead frame body is
An underlayer is formed by coating with at least one metal selected from the group consisting of n, Sn, Pb, In, Co, and Cd or an alloy thereof or an alloy of the above metal and Cu, and then,
The surface of the underlayer is coated with Ni to form an intermediate layer, and finally, the surface of the intermediate layer is coated with at least one metal selected from the group of Pd, Au, Ag, and Pt or alloys thereof. A method of manufacturing a lead frame for mounting a semiconductor chip is provided, which comprises forming the uppermost layer.

【0014】本発明のリードフレームでは、リードフレ
ーム本体の全面に、後述する下地層,中間層,最上層が
順次形成されている。リードフレーム本体の構成材料と
しては、従来から用いられている材料であれば何であっ
てもよく、例えば、Fe−42%Ni合金や、Cu−0.
3%Cr−0.25%Sn−0.2%Zn合金などをあげる
ことができる。なお、リードフレーム本体としては、そ
の表面に、更に、厚み0.02〜0.2μm程度のCuスト
ライクめっきを施しておくと、上述の下地層との密着性
の向上を図ることができる。
In the lead frame of the present invention, a base layer, an intermediate layer, and an uppermost layer, which will be described later, are sequentially formed on the entire surface of the lead frame body. The lead frame body may be made of any material that has been conventionally used, for example, Fe-42% Ni alloy or Cu-0.
3% Cr-0.25% Sn-0.2% Zn alloy etc. can be mentioned. If the surface of the lead frame body is further subjected to Cu strike plating with a thickness of about 0.02 to 0.2 μm, the adhesion with the above-mentioned underlayer can be improved.

【0015】このリードフレーム本体の全面に形成され
る下地層は、Zn,Sn,Pb,In,Co,Cdの群
から選ばれるいずれか1種の金属もしくはそれらの合金
またはこれらとCuとの合金から成り、リードフレーム
本体の腐食を防止するために設けられている層であり、
その厚みは、0.01〜0.2μmの範囲にあることが好ま
しい。
The underlayer formed on the entire surface of the lead frame body is a metal selected from the group consisting of Zn, Sn, Pb, In, Co and Cd, an alloy thereof, or an alloy of these and Cu. Is a layer that is provided to prevent corrosion of the lead frame body,
Its thickness is preferably in the range of 0.01 to 0.2 μm.

【0016】この厚みが0.01μmより薄い場合は、ピ
ンホールの多発に伴ってリードフレーム本体への充分な
耐食性が確保されず、また、0.2μmより厚い場合は、
耐食性確保の点では問題はないが、しかし、リードフレ
ーム本体や、この下地層の上に形成される中間層との密
着性が悪くなり、剥離傾向がでてくるからである。とく
に好ましい厚みは、0.05〜0.1μmである。
If the thickness is less than 0.01 μm, sufficient corrosion resistance to the lead frame body cannot be ensured due to frequent occurrence of pinholes, and if it is thicker than 0.2 μm,
This is because there is no problem in terms of ensuring corrosion resistance, but the adhesiveness between the lead frame body and the intermediate layer formed on the underlayer becomes poor, and a peeling tendency tends to occur. A particularly preferred thickness is 0.05 to 0.1 μm.

【0017】この下地層の上に形成される中間層はNi
から成り、下地層と一緒になってリードフレーム本体の
腐食を防止するとともに、例えばボンディング時の熱に
よって、リードフレーム本体の金属がこの中間層の上に
形成される最上層へ拡散してくることを防止するために
設けられる層である。中間層のこの働きによって、最上
層の厚みは0.2μm以下に設定することができるように
なる。
The intermediate layer formed on this underlayer is Ni.
The lead frame body, together with the underlayer, prevents corrosion of the lead frame body, and the metal of the lead frame body diffuses to the uppermost layer formed on this intermediate layer due to, for example, heat during bonding. This is a layer provided to prevent This function of the intermediate layer allows the thickness of the uppermost layer to be set to 0.2 μm or less.

【0018】中間層の厚みは、0.05〜2.0μmの範囲
に設定することが好ましい。この厚みが0.05μmより
薄くなると、リードフレーム本体への充分な耐食性を確
保できなくなり、また2.0μmより厚くなると、アウタ
ーリードの曲げ加工時にクラックが発生するようになる
からである。とくに好ましい厚みは、0.2〜1.0μmで
ある。
The thickness of the intermediate layer is preferably set in the range of 0.05 to 2.0 μm. If the thickness is thinner than 0.05 μm, sufficient corrosion resistance to the lead frame body cannot be secured, and if it is thicker than 2.0 μm, cracks will occur during bending of the outer leads. A particularly preferable thickness is 0.2 to 1.0 μm.

【0019】最上層は、Pd,Au,Ag,Ptのいず
れか1種またはそれらの合金から成り、リードフレーム
の保管時または加熱時におけるリードフレーム本体の酸
化を抑制するとともに、ワイヤとのボンディング性,半
田付け性および封止樹脂との密着性を高めるために設け
られる層である。この最上層の厚みは0.01〜0.2μm
の範囲内に設定することが好ましい。この厚みが0.01
μmより薄くなると、上記した機能は充分に発揮され
ず、また0.2μmより厚くなると、全体の価格は、従来
のAgのスポットめっきの場合よりも高価となってしま
うからである。とくに好ましい厚みは0.02〜0.15μ
mである。
The uppermost layer is made of any one of Pd, Au, Ag, and Pt or alloys thereof, and suppresses oxidation of the lead frame body during storage or heating of the lead frame and bondability with wires. , A layer provided to enhance solderability and adhesion to the sealing resin. The thickness of this uppermost layer is 0.01-0.2 μm
It is preferable to set within the range. This thickness is 0.01
This is because if the thickness is less than μm, the above-mentioned function is not fully exhibited, and if the thickness is more than 0.2 μm, the overall price becomes higher than that of the conventional Ag spot plating. Particularly preferred thickness is 0.02 to 0.15μ
m.

【0020】本発明のリードフレームは、リードフレー
ム本体の表面を、下地層,中間層および最上層で順次被
覆して製造することができる。この場合、各層の形成に
は、電気めっき法,無電解めっき法,または、PVD
法,CVD法のような乾式めっき法を適用することがで
きる。これら方法のうち、電気めっき法は、量産性に優
れているという点で好適である。
The lead frame of the present invention can be manufactured by sequentially covering the surface of the lead frame body with an underlayer, an intermediate layer and an uppermost layer. In this case, each layer is formed by electroplating, electroless plating, or PVD.
Method, a dry plating method such as a CVD method can be applied. Among these methods, the electroplating method is suitable because it is excellent in mass productivity.

【0021】また、各層を合金で形成する場合には、常
用の合金めっき法を適用してもよいが、次のような熱拡
散処理法を適用することもできる。すなわち、目的とす
る合金組成となるように、各単体金属の層を例えば電気
めっき法で形成したのち、全体を所定の条件下で熱処理
し、各単体金属を相互に拡散させる。この場合の熱処理
条件は、合金組成との関係で変化するが、概ね、温度2
00〜500℃,時間数秒〜1時間である。
When each layer is formed of an alloy, a conventional alloy plating method may be applied, but the following thermal diffusion treatment method can also be applied. That is, a layer of each elemental metal is formed by, for example, electroplating so as to have a desired alloy composition, and then the whole is heat-treated under predetermined conditions to diffuse each elemental metal into each other. The heat treatment conditions in this case change depending on the alloy composition, but the temperature is generally 2
The temperature is from 00 to 500 ° C. and the time is from several seconds to one hour.

【0022】また、この熱拡散処理は、各単体金属層の
形成後、所定の熱処理炉で行ってもよいが、半導体チッ
プ実装時におけるワイヤボンディングの熱によって行っ
てもよい。
The thermal diffusion treatment may be performed in a predetermined heat treatment furnace after forming each single metal layer, or may be performed by heat of wire bonding when mounting a semiconductor chip.

【0023】[0023]

【実施例】【Example】

実施例1 Cu−0.3%Cr−0.25%Sn−0.2%Zn合金条を
プレス加工して図1で示した形状のDIP(デュアルイ
ンラインパッケージ)型リードフレーム本体とした。
Example 1 A Cu-0.3% Cr-0.25% Sn-0.2% Zn alloy strip was pressed to obtain a DIP (dual inline package) type leadframe body having the shape shown in FIG.

【0024】このリードフレーム本体に、浴組成:ホウ
フッ化第一すず200g/l,第一すず濃度81g/
l,遊離ホウ酸25g/l,ゼラチン6g/l,βナフ
トール1g/l,浴温:20℃,電流密度:1A/dm
2 の条件で電気めっきを行い、厚み0.07μmのSnめ
っき層(下地層)を形成した。ついで、浴組成:スルフ
ァミン酸ニッケル600g/l,塩化ニッケル:10g
/l,ホウ酸40g/l,浴温:60℃,電流密度:1
0A/dm2 の条件下で、前記Snめっき層の上に、厚
み0.2μmのNiめっき層(中間層)を形成した。
In this lead frame body, a bath composition: 200 g / l of first tin borofluoride, 81 g / first tin concentration
1, free boric acid 25 g / l, gelatin 6 g / l, β-naphthol 1 g / l, bath temperature: 20 ° C., current density: 1 A / dm
Electroplating was performed under the conditions of 2 to form a Sn plating layer (base layer) having a thickness of 0.07 μm. Then, bath composition: nickel sulfamate 600 g / l, nickel chloride: 10 g
/ L, boric acid 40g / l, bath temperature: 60 ° C, current density: 1
A Ni plating layer (intermediate layer) having a thickness of 0.2 μm was formed on the Sn plating layer under the condition of 0 A / dm 2 .

【0025】最後に、浴組成:塩化パラジウム15g/
l,塩化アンモニウム30g/l,アンモニア(pH9
に調整),浴温:60℃,電流密度:2A/dm2 の条
件下で、前記Niめっき層の上に、厚み0.1μmのPd
めっき層を形成した。得られたリードフレームにつき、
下記の仕様で、ボンディング性,樹脂密着性,曲げ加工
時のクラック発生の有無,半田付け性,耐食性,めっき
密着性を調べた。
Finally, bath composition: palladium chloride 15 g /
1, ammonium chloride 30 g / l, ammonia (pH 9
Under the conditions of bath temperature: 60 ° C. and current density: 2 A / dm 2. Pd with a thickness of 0.1 μm is formed on the Ni plating layer.
A plating layer was formed. About the obtained lead frame,
The following specifications were examined for bondability, resin adhesion, presence of cracks during bending, solderability, corrosion resistance, and plating adhesion.

【0026】ボンディング性:パッド部に半導体チップ
を実装し、280℃,荷重50gのの条件で線径25μ
mのAu線をボンディングし、Au線をプル強度テスト
を行い、ワイヤ破断率(%)で評価した。 樹脂密着性 :エポキシ樹脂と熱圧着させてその剪断
強度を測定し、従来のAgスポットメッキのものと比較
して高強度である場合を○として評価した。
Bondability: A semiconductor chip is mounted on the pad portion, and the wire diameter is 25 μm under the conditions of 280 ° C. and load of 50 g.
m Au wire was bonded, and the Au wire was subjected to a pull strength test and evaluated by the wire breakage rate (%). Resin adhesion: Shear strength was measured by thermocompression bonding with epoxy resin, and when the strength was higher than that of conventional Ag spot plating, it was evaluated as ◯.

【0027】半田付け性 :230℃の共晶半田に3
秒間浸漬してそのときの半田濡れ面積を測定し、この面
積が95%以上の場合を○,95%未満の場合を×とし
て判定。 曲げ加工時のクラック発生の有無:アウターリードを、
R:0.4mmで90°に曲げ加工し、その加工部分を走査
電顕で観察して、クラックが発生していない場合を○,
クラックが発生している場合を×として判定。
Solderability: 3 for eutectic solder at 230 ° C
It is soaked for a second and the solder wet area at that time is measured. When this area is 95% or more, it is judged as ◯, and when it is less than 95%, it is judged as ×. Whether or not cracks occur during bending:
R: Bent to 90 ° with 0.4 mm, observe the processed part with a scanning electron microscope, and ○ when no cracks are generated.
When there is a crack, it is judged as ×.

【0028】耐食性 :5%塩化ナトリウム水溶
液をリードフレームに24時間噴霧し、リードフレーム
本体に錆が発生しない場合を○,錆が発生した場合を×
として判定。 めっき密着性 :アウターリードを180°密着曲げし
て曲げ戻したときに、めっきの剥離が認められない場合
を○,剥離が認められた場合を×として判定。 以上の結果を表1に示した。
Corrosion resistance: A 5% sodium chloride aqueous solution was sprayed on the lead frame for 24 hours, and when the rust did not occur on the lead frame body, ○, when rust occurred ×
Determined as. Plating Adhesion: When the outer lead is bent 180 ° and bent and then bent back, the case where the plating is not peeled is judged as ◯, and the case where the peeling is recognized is judged as ×. The above results are shown in Table 1.

【0029】実施例2 Fe−42%Ni合金条にエッチング加工を施して図1
で示した形状のDIP(デュアルインラインパッケー
ジ)型リードフレーム本体とした。このリードフレーム
本体に、浴組成:硫酸銅210g/l,硫酸52g/
l,浴温:30℃,電流密度:3A/dm2 の条件下で
電気めっきを行い、厚み0.2μmのCuめっき層(下地
層)を形成した。
EXAMPLE 2 An Fe-42% Ni alloy strip was subjected to an etching process, and FIG.
A DIP (dual in-line package) type lead frame body having the shape shown in FIG. In this lead frame body, bath composition: copper sulfate 210 g / l, sulfuric acid 52 g /
1, bath temperature: 30 ° C., current density: 3 A / dm 2 , electroplating was performed to form a Cu plating layer (base layer) having a thickness of 0.2 μm.

【0030】ついで、Zn濃度:8g/l,水酸化ナト
リウム濃度:80g/lのジンケート浴(浴温30℃)
を用い、電流密度0.5A/dm2 で、前記Cuめっき層
の上に厚み0.05μmのZnめっき層(下地層)を形成
した。その後、実施例1と同様の方法で、このZnめっ
き層の上に、厚み0.2μmのNiめっき層,厚み0.1μ
mのPdめっき層を順次形成し、最後に、全体を大気中
において、温度300℃で30秒間熱処理して、前記C
uめっき層とZnめっき層に熱拡散処理を施し、Cu−
Zn合金層を形成した。
Then, a zincate bath having a Zn concentration of 8 g / l and a sodium hydroxide concentration of 80 g / l (bath temperature 30 ° C.)
Was used to form a Zn plating layer (base layer) having a thickness of 0.05 μm on the Cu plating layer at a current density of 0.5 A / dm 2 . Then, in the same manner as in Example 1, a Ni plating layer having a thickness of 0.2 μm and a thickness of 0.1 μm was formed on the Zn plating layer.
m Pd plating layer is sequentially formed, and finally, the whole is heat-treated at a temperature of 300 ° C. for 30 seconds in the atmosphere to obtain the C
The u-plated layer and the Zn-plated layer are subjected to thermal diffusion treatment, and then Cu-
A Zn alloy layer was formed.

【0031】得られたリードフレームにつき、実施例1
と同様にして、各特性を測定し、その結果を表1に示し
た。 実施例3 実施例2で用いたリードフレーム本体に、浴組成:酸化
すずナトリウム67g/l,シアン化亜鉛:10g/
l,シアン化ナトリウム25g/l,水酸化ナトリウム
6g/l,浴温:65℃,電流密度:2A/dm2 の条
件下で厚み0.1μmのSn−Zn合金めっき層(下地
層)を形成した。
With respect to the obtained lead frame, Example 1
Each property was measured in the same manner as in, and the results are shown in Table 1. Example 3 In the lead frame body used in Example 2, bath composition: sodium tin oxide 67 g / l, zinc cyanide: 10 g / l
1, sodium cyanide 25 g / l, sodium hydroxide 6 g / l, bath temperature: 65 ° C., current density: 2 A / dm 2 under the condition of 0.1 μm thick Sn—Zn alloy plating layer (underlayer) did.

【0032】ついで、実施例1と同様の方法で、前記S
n−Zn合金めっき層の上に、厚み0.7μmのNiめっ
き層(中間層)と厚み0.05μmのPdめっき層(最上
層)を順次形成した。得られたリードフレームにつき、
実施例1の方法と同様にして各特性を測定した。その結
果を表1に示した。
Then, in the same manner as in Example 1, the S
A 0.7 μm thick Ni plating layer (intermediate layer) and a 0.05 μm thick Pd plating layer (uppermost layer) were sequentially formed on the n-Zn alloy plating layer. About the obtained lead frame,
Each property was measured in the same manner as in the method of Example 1. The results are shown in Table 1.

【0033】実施例4 Fe−42%Ni合金条にプレス加工を施して図1で示
した形状のリードフレーム本体とした。このリードフレ
ーム本体に、実施例2の場合と同じようにして、厚み0.
1μmのCuめっき層(下地層)を形成し、ついで、浴
組成:酸化カドミニウム25g/l,シアン化ナトリウ
ム100g/l,浴温:30℃,電流密度:0.5A/d
2 で、前記Cuめっき層の上に、厚み0.1μmのCd
めっき層(下地層)を形成した。
Example 4 An Fe-42% Ni alloy strip was pressed to obtain a lead frame body having the shape shown in FIG. The thickness of the lead frame body was set to 0.
A Cu plating layer (underlayer) of 1 μm is formed, and then bath composition: cadmium oxide 25 g / l, sodium cyanide 100 g / l, bath temperature: 30 ° C., current density: 0.5 A / d
m 2 above the Cu plating layer with a thickness of 0.1 μm of Cd
A plating layer (base layer) was formed.

【0034】その後、実施例1と同様の方法で、前記C
dめっき層の上に、厚み0.3μmのNiめっき層(中間
層)を形成し、更に、浴組成:シアン化金カリウム20
g/l,シアン化銀カリウム10g/l,シアン化カリ
ウム50g/l,チタニウム化合物2g/l,浴温:6
0℃,電流密度:2A/dm2 の条件下で、前記Niめ
っき層の上に、厚み0.05μmのAu−Ag合金めっき
層(最上層)を形成した。
Then, in the same manner as in Example 1, the C
A 0.3 μm-thick Ni plating layer (intermediate layer) is formed on the d plating layer, and the bath composition: potassium gold cyanide 20
g / l, potassium cyanide 10 g / l, potassium cyanide 50 g / l, titanium compound 2 g / l, bath temperature: 6
Under the condition of 0 ° C. and current density: 2 A / dm 2 , an Au—Ag alloy plating layer (uppermost layer) having a thickness of 0.05 μm was formed on the Ni plating layer.

【0035】得られたリードフレームにつき、実施例1
と同様にして、各特性を測定し、その結果を表1に示し
た。 実施例5 実施例2で用いたリードフレーム本体に、浴組成:塩化
インジウム35g/l,シアン化カリウム:150g/
l,水酸化カリウム35g/l,デキストリン35g/
l,浴温:20℃,電流密度:2A/dm2 の条件下で
厚み0.15μmのInめっき層(下地層)を形成した。
With respect to the obtained lead frame, Example 1
Each property was measured in the same manner as in, and the results are shown in Table 1. Example 5 In the lead frame body used in Example 2, bath composition: indium chloride 35 g / l, potassium cyanide: 150 g /
1, potassium hydroxide 35g / l, dextrin 35g /
1, a bath temperature: 20 ° C., and a current density: 2 A / dm 2 , an In plating layer (base layer) having a thickness of 0.15 μm was formed.

【0036】ついで、実施例1と同様の方法で、前記I
nめっき層の上に、厚み0.2μmのNiめっき層(中間
層)と厚み0.1μmのPdめっき層(最上層)を順次形
成した。得られたリードフレームにつき、実施例1の方
法と同様にして各特性を測定した。その結果を表1に示
した。
Then, in the same manner as in Example 1, the I
A 0.2 μm thick Ni plating layer (intermediate layer) and a 0.1 μm thick Pd plating layer (uppermost layer) were sequentially formed on the n plating layer. Each property of the obtained lead frame was measured in the same manner as in the method of Example 1. The results are shown in Table 1.

【0037】実施例6 Cu−0.3%Cr−0.25%Sn−0.2%Zn合金条に
エッチング加工を施して図1で示した形状のリードフレ
ーム本体とした。このリードフレーム本体に、実施例1
と同様にして、厚み0.05μmのSnめっき層(下地
層),厚み1.2μmのNiめっき層(中間層),厚み0.
1μmのPdめっき層(最上層)を順次形成し、つい
で、浴組成:シアン化金カリウム10g/l,シアン化
カリウム30g/l,炭酸カリウム30g/l,第二リ
ン酸カリウム30g/l,浴温:55℃,電流密度:0.
5A/dm2 の条件下で、前記Pdめっき層の上に、厚
み0.02μmのAuめっき層を形成した。
Example 6 A Cu-0.3% Cr-0.25% Sn-0.2% Zn alloy strip was etched to obtain a leadframe body having the shape shown in FIG. In this lead frame body,
In the same manner as in, 0.05 μm thick Sn plating layer (base layer), 1.2 μm thick Ni plating layer (intermediate layer), thickness 0.1 μm.
A 1 μm Pd plating layer (uppermost layer) was sequentially formed, and then bath composition: potassium gold cyanide 10 g / l, potassium cyanide 30 g / l, potassium carbonate 30 g / l, dibasic potassium phosphate 30 g / l, bath temperature: 55 ℃, current density: 0.
An Au plating layer having a thickness of 0.02 μm was formed on the Pd plating layer under the condition of 5 A / dm 2 .

【0038】得られたリードフレームのパッド部にSi
チップをダイボンディングし、更に、インナーリードと
の間をAu線でワイヤボンディングした。その後、リー
ドフレームの断面を調べたところ、リードフレーム本体
の表面はCu−Sn合金層であり、その上にNi層,更
にその上にはAu−Pd合金層が形成されていた。
Si is formed on the pad portion of the obtained lead frame.
The chip was die-bonded, and the inner lead was wire-bonded with an Au wire. After that, when the cross section of the lead frame was examined, the surface of the lead frame body was a Cu—Sn alloy layer, a Ni layer was formed thereon, and an Au—Pd alloy layer was further formed thereon.

【0039】このリードフレームにつき、実施例1と同
様にして、各特性を調べた。その結果を表1に示した。 実施例7 実施例2で用いたリードフレーム本体に、浴組成:塩基
性炭酸鉛150g/l,フッ化水素酸240g/l,ホ
ウ酸105g/l,にかわ0.2g/l,浴温:20℃,
電流密度:2A/dm2 の条件下で厚み0.15μmのP
bめっき層(下地層)を形成した。
The characteristics of this lead frame were examined in the same manner as in Example 1. The results are shown in Table 1. Example 7 In the lead frame body used in Example 2, the bath composition: basic lead carbonate 150 g / l, hydrofluoric acid 240 g / l, boric acid 105 g / l, glue 0.2 g / l, bath temperature: 20 ℃,
Current density: P of 0.15 μm thickness under the condition of 2 A / dm 2.
A b-plated layer (base layer) was formed.

【0040】ついで、実施例1と同様の方法で、前記P
bめっき層の上に、厚み0.1μmのNiめっき層(中間
層)を形成し、更に、浴組成:塩化白金酸アンモニウム
15g/l,水酸化ナトリウム20g/l,塩化アンモ
ニウム5g/l,クエン酸90g/l,浴温:80℃,
電流密度:0.2A/dm2 の条件下で、前記Niめっき
層の上に、厚み0.15μmのPtめっき層(最上層)を
形成した。
Then, in the same manner as in Example 1, the P
A 0.1 μm thick Ni plating layer (intermediate layer) is formed on the b plating layer, and the bath composition: ammonium chloroplatinate 15 g / l, sodium hydroxide 20 g / l, ammonium chloride 5 g / l, quench Acid 90g / l, bath temperature: 80 ° C,
Under the condition of current density: 0.2 A / dm 2 , a Pt plating layer (uppermost layer) having a thickness of 0.15 μm was formed on the Ni plating layer.

【0041】得られたリードフレームにつき、実施例1
の方法と同様にして、各特性を測定した。その結果を表
1に示した。 実施例8 実施例1で用いたリードフレーム本体に、浴組成:硫酸
コバルト504g/l,塩化ナトリウム17g/l,ホ
ウ酸45g/l,浴温:20℃,電流密度:4A/dm
2 の条件下で厚み0.1μmのCoめっき層(下地層)を
形成した。
With respect to the obtained lead frame, Example 1
Each property was measured in the same manner as the method of. The results are shown in Table 1. Example 8 In the lead frame body used in Example 1, bath composition: cobalt sulfate 504 g / l, sodium chloride 17 g / l, boric acid 45 g / l, bath temperature: 20 ° C., current density: 4 A / dm.
Under the conditions of 2 , a Co plating layer (underlayer) having a thickness of 0.1 μm was formed.

【0042】ついで、実施例1と同様の方法で、前記C
oめっき層の上に、厚み0.5μmのNiめっき層(中間
層)と厚み0.1μmのPdめっき層(最上層)を順次形
成した。得られたリードフレームにつき、実施例1の方
法と同様にして、各特性を測定した。その結果を表1に
示した。
Then, in the same manner as in Example 1, the C
On the o plating layer, a 0.5 μm thick Ni plating layer (intermediate layer) and a 0.1 μm thick Pd plating layer (uppermost layer) were sequentially formed. Each characteristic of the obtained lead frame was measured in the same manner as in the method of Example 1. The results are shown in Table 1.

【0043】比較例1 Snめっき層を形成することなく、実施例1のリードフ
レーム本体に、直接、実施例1の方法で厚み0.2μmの
Niめっき層,厚み0.1μmのPdめっき層を順次形成
してリードフレームとした。このリードフレームにつ
き、実施例1と同様の方法で、各特性を測定した。その
結果を表1に示した。
Comparative Example 1 The lead frame body of Example 1 was directly coated with a Ni plating layer having a thickness of 0.2 μm and a Pd plating layer having a thickness of 0.1 μm by the method of Example 1 without forming an Sn plating layer. It was sequentially formed into a lead frame. Each characteristic of this lead frame was measured in the same manner as in Example 1. The results are shown in Table 1.

【0044】比較例2 実施例1のリードフレーム本体に、実施例1と同じよう
な方法で、厚み0.5μmのSnめっき層,厚み0.2μm
のNiめっき層,厚み0.1μmのPdめっき層を順次形
成したのち、全体を、大気中において、温度300℃で
30秒間熱処理した。
Comparative Example 2 In the same manner as in Example 1, the lead frame main body of Example 1 was coated with a Sn plating layer having a thickness of 0.5 μm and a thickness of 0.2 μm.
After the Ni plating layer and the Pd plating layer having a thickness of 0.1 μm were sequentially formed, the whole was heat-treated at a temperature of 300 ° C. for 30 seconds in the atmosphere.

【0045】得られたリードフレームにつき、実施例1
と同様の方法で各特性を測定した。その結果を表1に示
した。 比較例3 実施例2のリードフレーム本体に、実施例2と同じよう
な方法で厚み0.1μmのCuめっき層を形成し、つい
で、実施例1と同じようにして、このCuめっき層の上
に、厚み5μmのNiめっき層,厚み0.1μmのPdめ
っき層を順次形成した。
With respect to the obtained lead frame, Example 1
Each property was measured by the same method as in. The results are shown in Table 1. Comparative Example 3 On the lead frame body of Example 2, a Cu plating layer having a thickness of 0.1 μm was formed in the same manner as in Example 2, and then, in the same manner as in Example 1, the Cu plating layer was formed on the Cu plating layer. Then, a Ni plating layer having a thickness of 5 μm and a Pd plating layer having a thickness of 0.1 μm were sequentially formed.

【0046】得られたリードフレームにつき、実施例1
と同様にして各特性を測定した。その結果を表1に示し
た。 比較例4 実施例2のリードフレーム本体に、実施例2と同じよう
な方法で厚み0.1μmのCuめっき層を形成し、つい
で、実施例1と同じようにして、このCuめっき層の上
に、厚み0.03μmのNiめっき層,厚み0.005μm
のPdめっき層を順次形成した。
With respect to the obtained lead frame, Example 1
Each property was measured in the same manner as in. The results are shown in Table 1. Comparative Example 4 On the lead frame body of Example 2, a Cu plating layer having a thickness of 0.1 μm was formed in the same manner as in Example 2, and then on the Cu plating layer in the same manner as in Example 1. Ni plating layer with a thickness of 0.03 μm and a thickness of 0.005 μm
Pd plating layers of were sequentially formed.

【0047】得られたリードフレームにつき、実施例1
と同様にして各特性を測定した。その結果を表1に示し
た。
With respect to the obtained lead frame, Example 1
Each property was measured in the same manner as in. The results are shown in Table 1.

【0048】[0048]

【表1】 [Table 1]

【0049】[0049]

【発明の効果】以上の説明で明らかなように、本発明の
リードフレームは、ワイヤボンディング性,半田付け
性,封止樹脂との密着性,耐食性,めっきの密着性がい
ずれも優れており、また、アウターリードの曲げ加工を
行った場合でもクラックは発生しない。
As is clear from the above description, the lead frame of the present invention is excellent in wire bonding property, soldering property, adhesion with sealing resin, corrosion resistance, and plating adhesion. In addition, even when the outer leads are bent, cracks do not occur.

【0050】しかも、Pdなどの貴金属から成る最上層
の厚みは、0.2μmより薄くてもよいので、そのコスト
は低減される。このような優れた効果は、リードフレー
ム本体と中間層との間に下地層を介在させることによ
り、中間層と下地層との共同の働きで耐食性が向上する
とともに、中間層であるNiめっき層を薄くすることが
可能になるため、曲げ加工性の向上ももたらされるから
である。そして、中間層と下地層が上記機能を果たすこ
とにより、最上層の貴金属層を薄くすることが可能にな
る。
Moreover, since the thickness of the uppermost layer made of a noble metal such as Pd may be thinner than 0.2 μm, its cost is reduced. Such an excellent effect is that by interposing an underlayer between the lead frame body and the intermediate layer, the corrosion resistance is improved by the joint action of the intermediate layer and the underlayer, and at the same time, the Ni plating layer which is the intermediate layer. This is because it is possible to make the thickness thinner, which also improves the bending workability. Then, the intermediate layer and the underlayer perform the above-mentioned functions, so that the uppermost noble metal layer can be thinned.

【図面の簡単な説明】[Brief description of drawings]

【図1】リードフレーム本体の平面図である。FIG. 1 is a plan view of a lead frame body.

【図2】リードフレーム本体に半導体チップを実装した
状態を示す断面図である。
FIG. 2 is a sectional view showing a state in which a semiconductor chip is mounted on a lead frame body.

【符号の説明】[Explanation of symbols]

1 パッド部 2 インナーリード 3 ダイバー部 4 アウターリード 5 接着剤 6 半導体チップ 7 電極パッド 8 ワイヤ 9 封止樹脂 1 Pad Part 2 Inner Lead 3 Diver Part 4 Outer Lead 5 Adhesive 6 Semiconductor Chip 7 Electrode Pad 8 Wire 9 Sealing Resin

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 リードフレーム本体と、前記リードフレ
ーム本体の上に形成されて成る、Zn,Sn,Pb,I
n,Co,Cdの群から選ばれる少なくとも1種の金属
もしくはそれらの合金または前記金属とCuとの合金の
下地層と、前記下地層の上に形成されて成る、Niの中
間層と、前記中間層の上に形成されて成る、Pd,A
u,Ag,Ptの群から選ばれる少なくとも1種の金属
またはそれらの合金の最上層とを備えていることを特徴
とする半導体チップ実装用リードフレーム。
1. A lead frame body and Zn, Sn, Pb, I formed on the lead frame body.
an underlayer of at least one metal selected from the group consisting of n, Co, and Cd or an alloy thereof or an alloy of the above metal and Cu; and a Ni intermediate layer formed on the underlayer; Pd, A formed on the intermediate layer
A lead frame for mounting a semiconductor chip, comprising a top layer of at least one metal selected from the group of u, Ag, and Pt or an alloy thereof.
【請求項2】 前記下地層の厚みが0.01〜0.2μm,
前記中間層の厚みが0.05〜2.0μm,前記最上層の厚
みが0.01〜0.2μmである請求項1の半導体チップ実
装用リードフレーム。
2. The thickness of the underlayer is 0.01 to 0.2 μm,
2. The lead frame for mounting a semiconductor chip according to claim 1, wherein the intermediate layer has a thickness of 0.05 to 2.0 [mu] m and the uppermost layer has a thickness of 0.01 to 0.2 [mu] m.
【請求項3】 リードフレーム本体の全面を、Zn,S
n,Pb,In,Co,Cdの群から選ばれる少なくと
も1種の金属もしくはそれらの合金または前記金属とC
uとの合金で被覆して下地層を形成し、ついで、前記下
地層の表面をNiで被覆して中間層を形成し、最後に、
前記中間層の表面を、Pd,Au,Ag,Ptの群から
選ばれる少なくとも1種の金属またはそれらの合金で被
覆して最上層を形成することを特徴とする半導体チップ
実装用リードフレームの製造方法。
3. The entire surface of the lead frame body is coated with Zn, S.
at least one metal selected from the group consisting of n, Pb, In, Co and Cd, an alloy thereof, or the above metal and C
to form an underlayer by coating with an alloy with u, and then to coat the surface of the underlayer with Ni to form an intermediate layer, and finally,
Manufacturing of a lead frame for mounting a semiconductor chip, characterized in that the uppermost layer is formed by coating the surface of the intermediate layer with at least one metal selected from the group of Pd, Au, Ag and Pt or alloys thereof. Method.
【請求項4】 前記各層の被覆形成は電気めっき法で行
われる請求項3の半導体チップ実装用リードフレームの
製造方法。
4. The method for manufacturing a lead frame for mounting a semiconductor chip according to claim 3, wherein the coating of each layer is formed by an electroplating method.
【請求項5】 前記下地層または/および前記最上層
が、合金層である請求項3の半導体チップ実装用リード
フレームの製造方法。
5. The method of manufacturing a lead frame for mounting a semiconductor chip according to claim 3, wherein the underlayer and / or the uppermost layer is an alloy layer.
【請求項6】 前記合金層が合金めっき法で形成される
請求項5の半導体チップ実装用リードフレームの製造方
法。
6. The method for manufacturing a lead frame for mounting a semiconductor chip according to claim 5, wherein the alloy layer is formed by an alloy plating method.
【請求項7】 前記合金層が、熱拡散処理によって形成
される請求項5の半導体チップ実装用リードフレームの
製造方法。
7. The method for manufacturing a lead frame for mounting a semiconductor chip according to claim 5, wherein the alloy layer is formed by thermal diffusion treatment.
【請求項8】 前記熱拡散処理が、半導体チップの実装
時におけるボンディング過程の熱によって行われる請求
項7の半導体実装用リードフレームの製造方法。
8. The method of manufacturing a lead frame for semiconductor mounting according to claim 7, wherein the thermal diffusion treatment is performed by heat of a bonding process when mounting a semiconductor chip.
JP3282608A 1991-10-29 1991-10-29 Lead frame for mounting semiconductor chip and method of manufacturing the same Expired - Fee Related JP2925815B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3282608A JP2925815B2 (en) 1991-10-29 1991-10-29 Lead frame for mounting semiconductor chip and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3282608A JP2925815B2 (en) 1991-10-29 1991-10-29 Lead frame for mounting semiconductor chip and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH05117898A true JPH05117898A (en) 1993-05-14
JP2925815B2 JP2925815B2 (en) 1999-07-28

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Application Number Title Priority Date Filing Date
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Country Link
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0621633A2 (en) * 1993-04-10 1994-10-26 W.C. Heraeus GmbH Leadframe for integrated circuits
WO1996034412A1 (en) * 1995-04-27 1996-10-31 National Semiconductor Corporation Protective coating combination for lead frames
WO2002025702A2 (en) * 2000-09-20 2002-03-28 Kim Stephen M Semiconductor product with a silver and gold alloy
US6521358B1 (en) 1997-03-04 2003-02-18 Matsushita Electric Industrial Co., Ltd. Lead frame for semiconductor device and method of producing same
US6593643B1 (en) * 1999-04-08 2003-07-15 Shinko Electric Industries Co., Ltd. Semiconductor device lead frame
JP2006088451A (en) * 2004-09-22 2006-04-06 Rikogaku Shinkokai Pt base conductive coating material excellent in secular deterioration characteristic resistance
JP2007158327A (en) * 2005-12-01 2007-06-21 Asm Assembly Automation Ltd Leadframe provided with tin plating, or intermetallic layer formed of tin plating
JP2007284762A (en) * 2006-04-18 2007-11-01 Sumitomo Metal Mining Co Ltd Method for forming tin-plated film, and semiconductor device
US8016624B2 (en) * 2005-09-22 2011-09-13 Enplas Corporation Electric contact and socket for electrical part
JP2012046827A (en) * 2011-11-18 2012-03-08 Fujitsu Ltd Plating coating, method of forming the same, and electronic part

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0621633A2 (en) * 1993-04-10 1994-10-26 W.C. Heraeus GmbH Leadframe for integrated circuits
EP0621633A3 (en) * 1993-04-10 1995-01-11 Heraeus Gmbh W C Leadframe for integrated circuits.
US5486721A (en) * 1993-04-10 1996-01-23 W.C. Heraeus Gmbh Lead frame for integrated circuits
WO1996034412A1 (en) * 1995-04-27 1996-10-31 National Semiconductor Corporation Protective coating combination for lead frames
US6521358B1 (en) 1997-03-04 2003-02-18 Matsushita Electric Industrial Co., Ltd. Lead frame for semiconductor device and method of producing same
US6593643B1 (en) * 1999-04-08 2003-07-15 Shinko Electric Industries Co., Ltd. Semiconductor device lead frame
WO2002025702A3 (en) * 2000-09-20 2002-08-01 Stephen M Kim Semiconductor product with a silver and gold alloy
WO2002025702A2 (en) * 2000-09-20 2002-03-28 Kim Stephen M Semiconductor product with a silver and gold alloy
JP2006088451A (en) * 2004-09-22 2006-04-06 Rikogaku Shinkokai Pt base conductive coating material excellent in secular deterioration characteristic resistance
US8016624B2 (en) * 2005-09-22 2011-09-13 Enplas Corporation Electric contact and socket for electrical part
USRE45924E1 (en) * 2005-09-22 2016-03-15 Enplas Corporation Electric contact and socket for electrical part
JP2007158327A (en) * 2005-12-01 2007-06-21 Asm Assembly Automation Ltd Leadframe provided with tin plating, or intermetallic layer formed of tin plating
JP2007284762A (en) * 2006-04-18 2007-11-01 Sumitomo Metal Mining Co Ltd Method for forming tin-plated film, and semiconductor device
JP2012046827A (en) * 2011-11-18 2012-03-08 Fujitsu Ltd Plating coating, method of forming the same, and electronic part

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