JP7401430B2 - 記憶装置および電子機器 - Google Patents

記憶装置および電子機器 Download PDF

Info

Publication number
JP7401430B2
JP7401430B2 JP2020524946A JP2020524946A JP7401430B2 JP 7401430 B2 JP7401430 B2 JP 7401430B2 JP 2020524946 A JP2020524946 A JP 2020524946A JP 2020524946 A JP2020524946 A JP 2020524946A JP 7401430 B2 JP7401430 B2 JP 7401430B2
Authority
JP
Japan
Prior art keywords
transistor
conductive layer
insulating layer
region
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2020524946A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2019243957A5 (https=
JPWO2019243957A1 (ja
Inventor
貴彦 石津
利彦 齋藤
秀貴 魚地
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Publication of JPWO2019243957A1 publication Critical patent/JPWO2019243957A1/ja
Publication of JPWO2019243957A5 publication Critical patent/JPWO2019243957A5/ja
Priority to JP2023206826A priority Critical patent/JP2024019354A/ja
Application granted granted Critical
Publication of JP7401430B2 publication Critical patent/JP7401430B2/ja
Priority to JP2025094165A priority patent/JP2025124855A/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419Read-write [R-W] circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4097Bit-line organisation, e.g. bit-line layout, folded bit lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/14Word line organisation; Word line lay-out
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/16Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48Data lines or contacts therefor
    • H10B12/482Bit lines
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48Data lines or contacts therefor
    • H10B12/488Word lines
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H10D30/6756Amorphous oxide semiconductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40Crystalline structures
    • H10D62/405Orientations of crystalline planes
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4094Bit-line management or control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Dram (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2020524946A 2018-06-22 2019-06-13 記憶装置および電子機器 Active JP7401430B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2023206826A JP2024019354A (ja) 2018-06-22 2023-12-07 記憶装置
JP2025094165A JP2025124855A (ja) 2018-06-22 2025-06-05 記憶装置

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2018118869 2018-06-22
JP2018118869 2018-06-22
JP2018124319 2018-06-29
JP2018124319 2018-06-29
PCT/IB2019/054931 WO2019243957A1 (ja) 2018-06-22 2019-06-13 記憶装置および電子機器

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2023206826A Division JP2024019354A (ja) 2018-06-22 2023-12-07 記憶装置

Publications (3)

Publication Number Publication Date
JPWO2019243957A1 JPWO2019243957A1 (ja) 2021-07-08
JPWO2019243957A5 JPWO2019243957A5 (https=) 2022-06-02
JP7401430B2 true JP7401430B2 (ja) 2023-12-19

Family

ID=68983796

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2020524946A Active JP7401430B2 (ja) 2018-06-22 2019-06-13 記憶装置および電子機器
JP2023206826A Withdrawn JP2024019354A (ja) 2018-06-22 2023-12-07 記憶装置
JP2025094165A Pending JP2025124855A (ja) 2018-06-22 2025-06-05 記憶装置

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP2023206826A Withdrawn JP2024019354A (ja) 2018-06-22 2023-12-07 記憶装置
JP2025094165A Pending JP2025124855A (ja) 2018-06-22 2025-06-05 記憶装置

Country Status (5)

Country Link
US (2) US11443796B2 (https=)
JP (3) JP7401430B2 (https=)
KR (2) KR20250130429A (https=)
CN (2) CN121442688A (https=)
WO (1) WO2019243957A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12439581B2 (en) * 2019-12-27 2025-10-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
CN115568206A (zh) * 2021-07-02 2023-01-03 长鑫存储技术有限公司 存储单元及其制备方法、存储器及其制备方法
CN117479527A (zh) * 2022-09-21 2024-01-30 北京超弦存储器研究院 一种存储结构、电子设备

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006294116A (ja) 2005-04-08 2006-10-26 Renesas Technology Corp 半導体記憶装置
JP2008311641A (ja) 2007-05-17 2008-12-25 Elpida Memory Inc 半導体記憶装置及びその製造方法
JP2012256830A (ja) 2010-12-28 2012-12-27 Semiconductor Energy Lab Co Ltd 記憶装置
JP2015181159A (ja) 2014-03-07 2015-10-15 株式会社半導体エネルギー研究所 半導体装置
JP2016076285A (ja) 2014-10-06 2016-05-12 株式会社半導体エネルギー研究所 半導体装置及び電子機器
JP2017016730A (ja) 2010-05-20 2017-01-19 株式会社半導体エネルギー研究所 半導体装置の駆動方法
JP2018085357A (ja) 2016-11-21 2018-05-31 株式会社半導体エネルギー研究所 記憶装置、及び電子機器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003017487A (ja) * 2001-06-29 2003-01-17 Rohm Co Ltd 半導体装置およびその製造方法
JP3934507B2 (ja) * 2002-08-08 2007-06-20 株式会社東芝 半導体記憶装置および半導体記憶装置の製造方法
JP5086625B2 (ja) * 2006-12-15 2012-11-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
TWI555128B (zh) 2010-08-06 2016-10-21 半導體能源研究所股份有限公司 半導體裝置及半導體裝置的驅動方法
JP2015018940A (ja) * 2013-07-11 2015-01-29 ルネサスエレクトロニクス株式会社 半導体装置
WO2017111798A1 (en) * 2015-12-23 2017-06-29 Intel Corporation High retention time memory element with dual gate devices
KR102473660B1 (ko) * 2016-02-22 2022-12-02 삼성전자주식회사 메모리 소자 및 그 제조 방법
KR102330605B1 (ko) * 2016-06-22 2021-11-24 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006294116A (ja) 2005-04-08 2006-10-26 Renesas Technology Corp 半導体記憶装置
JP2008311641A (ja) 2007-05-17 2008-12-25 Elpida Memory Inc 半導体記憶装置及びその製造方法
JP2017016730A (ja) 2010-05-20 2017-01-19 株式会社半導体エネルギー研究所 半導体装置の駆動方法
JP2012256830A (ja) 2010-12-28 2012-12-27 Semiconductor Energy Lab Co Ltd 記憶装置
JP2015181159A (ja) 2014-03-07 2015-10-15 株式会社半導体エネルギー研究所 半導体装置
JP2016076285A (ja) 2014-10-06 2016-05-12 株式会社半導体エネルギー研究所 半導体装置及び電子機器
JP2018085357A (ja) 2016-11-21 2018-05-31 株式会社半導体エネルギー研究所 記憶装置、及び電子機器

Also Published As

Publication number Publication date
CN112313792B (zh) 2025-12-16
JP2024019354A (ja) 2024-02-08
US11443796B2 (en) 2022-09-13
US11922999B2 (en) 2024-03-05
WO2019243957A1 (ja) 2019-12-26
CN112313792A (zh) 2021-02-02
KR20210022041A (ko) 2021-03-02
CN121442688A (zh) 2026-01-30
KR102851545B1 (ko) 2025-08-28
US20230005528A1 (en) 2023-01-05
US20210257020A1 (en) 2021-08-19
KR20250130429A (ko) 2025-09-01
JPWO2019243957A1 (ja) 2021-07-08
JP2025124855A (ja) 2025-08-26

Similar Documents

Publication Publication Date Title
KR102637749B1 (ko) 반도체 장치 및 반도체 장치의 제작 방법
CN112368846A (zh) 半导体装置及半导体装置的制造方法
KR102602338B1 (ko) 기억 장치
JP2024019354A (ja) 記憶装置
JP2024052817A (ja) 半導体装置
US11462538B2 (en) Semiconductor device
US12604498B2 (en) Memory device
TW202025447A (zh) 半導體裝置
WO2024116037A1 (ja) 半導体装置
US12159941B2 (en) Transistor and electronic device
JP7322008B2 (ja) 半導体装置
US12142693B2 (en) Semiconductor device
JP7171226B2 (ja) 記憶装置
WO2024089571A1 (ja) 半導体装置、半導体装置の作製方法、及び電子機器
JP2025188139A (ja) 半導体装置の作製方法
WO2024100489A1 (ja) 半導体装置、半導体装置の作製方法、及び電子機器
WO2023148571A1 (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220525

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20220525

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20230606

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230726

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20231107

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20231207

R150 Certificate of patent or registration of utility model

Ref document number: 7401430

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150