JP7355393B2 - 半導体デバイスを形成する方法および半導体デバイス - Google Patents

半導体デバイスを形成する方法および半導体デバイス Download PDF

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JP7355393B2
JP7355393B2 JP2020532918A JP2020532918A JP7355393B2 JP 7355393 B2 JP7355393 B2 JP 7355393B2 JP 2020532918 A JP2020532918 A JP 2020532918A JP 2020532918 A JP2020532918 A JP 2020532918A JP 7355393 B2 JP7355393 B2 JP 7355393B2
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energy barrier
forming
layer
semiconductor
fet
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JP2021507519A5 (enExample
JP2021507519A (ja
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リ、ユーロン
ソロモン、ポール、マイケル
コスワッタ、シユランガ
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International Business Machines Corp
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  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2020532918A 2017-12-21 2018-12-19 半導体デバイスを形成する方法および半導体デバイス Active JP7355393B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/850,098 2017-12-21
US15/850,098 US10374041B2 (en) 2017-12-21 2017-12-21 Field effect transistor with controllable resistance
PCT/IB2018/060321 WO2019123303A1 (en) 2017-12-21 2018-12-19 Field effect transistor with controllable resistance

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JP2021507519A JP2021507519A (ja) 2021-02-22
JP2021507519A5 JP2021507519A5 (enExample) 2021-04-01
JP7355393B2 true JP7355393B2 (ja) 2023-10-03

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US (5) US10374041B2 (enExample)
JP (1) JP7355393B2 (enExample)
CN (1) CN111512438B (enExample)
DE (1) DE112018005614B4 (enExample)
GB (1) GB2583299B (enExample)
WO (1) WO2019123303A1 (enExample)

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