US7067381B1 - Structure and method to reduce drain induced barrier lowering - Google Patents
Structure and method to reduce drain induced barrier lowering Download PDFInfo
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- US7067381B1 US7067381B1 US10/636,336 US63633603A US7067381B1 US 7067381 B1 US7067381 B1 US 7067381B1 US 63633603 A US63633603 A US 63633603A US 7067381 B1 US7067381 B1 US 7067381B1
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 230000004888 barrier function Effects 0.000 title claims description 7
- 239000007943 implant Substances 0.000 claims abstract description 63
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 13
- 229910052796 boron Inorganic materials 0.000 claims description 13
- 229910052785 arsenic Inorganic materials 0.000 claims description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 7
- 239000002245 particle Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims 4
- 239000002019 doping agent Substances 0.000 description 15
- 230000008569 process Effects 0.000 description 12
- 238000012545 processing Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 5
- 238000013459 approach Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000002939 deleterious effect Effects 0.000 description 3
- 238000005755 formation reaction Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005381 potential energy Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Definitions
- the present invention relates to the manufacture of an integrated circuit. More specifically, embodiments of the present invention relate to the formation of an n-channel and/or p-channel asymmetrical transistor using an arsenic drain side implantation to reduce DIBL.
- Moore's Law states that the number of semiconductor devices, (e.g., transistors), per unit area will double every 18–24 months. While other factors such as design improvements contribute to the rapid growth, one of the fundamental drivers of this inexorable density increase is the ever-shrinking minimum feature size of semiconductors. For example, a common minimum feature size of modern semiconductors is 0.15 microns.
- a modern integrated circuit, for example a flash memory device may have millions to hundreds of millions of devices made up of complex, multi-layered structures that are fabricated through hundreds of processing steps.
- Those structures, for example a gate stack are formed by repeated deposition and patterning of thin films on a silicon substrate, also known as a wafer.
- SCE short channel effects
- the distance between source and drain implants is often referred to as the physical channel length.
- distance between the source and drains regions becomes less than the physical channel length and is often referred to as the effective channel length (Leff).
- Leff effective channel length
- SCE impacts device operation by, inter alia, reducing device threshold voltages and increasing sub-threshold currents.
- Leff becomes quite small, the depletion regions associated with the source and drain areas may extend toward one another and substantially occupy the channel area. Hence, some of the channel will be partially depleted without any influence of gate voltage. As a result, less gate bias is required to invert the channel of a transistor having a short Leff.
- threshold voltage lowering is the concept of subthreshold current flow. Even when the gate voltage is below the threshold amount, current between the source and drain nonetheless exist.
- DIBL drain-induced barrier lowering
- One method in which to control SCE is to increase the dopant concentration within the body of the device.
- increasing dopant within the body deleteriously increases potential gradients in the ensuing device. For example, increasing dopant causes a hotter junction and lowers the breakdown voltage.
- FIG. 1A depicts a conventional flash memory cell 10 during a pocket implant.
- the gate stack formed includes a floating gate 12 and a control gate 14 . Included are the source 16 and drain 18 .
- the channel 17 is between the source 16 and the drain 18 .
- the drain is masked by photoresist 19 .
- the drain is masked by photoresist to ensure that little of the dopant provided by a pocket implant reaches the portion of the channel 17 near the drain 18 .
- high DIBL results in current leakage during high voltage programming.
- dopant typically Boron
- FIG. 1B illustrates the memory cell 10 after an implant, subsequent thermal anneal and after removing photoresist 19 .
- a thermal anneal is used to drive the source side implant across the channel.
- the concentration of dopant is graded across the channel length. The highest concentration is near the source and then the concentration tapers off towards the drain side.
- the memory cell 10 may have fewer short channel effects and DIBL can be reduced.
- FIG. 2 illustrates a graph 20 depicting channel dopant concentration 22 with respect to the length of the channel 24 .
- Channel length 28 illustrates a relatively large channel length and as a result of the relatively large channel length, the dopant concentration 22 is graded across the channel length. As mentioned above, with a relatively large channel length, a graded dopant concentration can be achieved using the above-mentioned method. As feature size continues to decrease, the channel length becomes smaller. Channel length 29 depicts a typical feature size that can be currently manufactured. As a result of the small channel length, the dopant concentration is virtually flat across the channel, thus resulting in poor reduction of DIBL.
- a properly designed transistor that overcomes the above problems must therefore be applicable to an n-channel transistor. That transistor must be one that is readily fabricated within existing process technologies.
- the structure and method for reducing DIBL should utilize established semiconductor manufacturing equipment.
- the structure and method for reducing DIBL should facilitate in maintaining precise critical dimensions for small-scale semiconductor manufacturing.
- Embodiments of the present invention include a method for manufacturing a transistor comprising forming a gate conductor above a semiconductor substrate, forming a lightly doped implant region within the substrate, wherein the lightly doped implant region is substantially on the source side of the transistor; and forming a counter doping implant region within the substrate, wherein the counter doping implant region is substantially on the drain side and wherein the counter doping reduces the net impurity concentration on the drain side
- Embodiments of the present invention also include a structure for reducing DIBL in a semiconductor comprising a gate conductor formed above a semiconductor substrate, a lightly doped implant region formed within the substrate, wherein the lightly doped implant region is substantially on the source side of the transistor; and a counter doping implant region formed within the substrate, wherein the counter doping implant region is substantially on the drain side and wherein the counter doping reduces the net impurity concentration on the drain side.
- FIG. 1A is an illustration of a conventional processing approach used to reduce DIBL illustrating a source implant.
- FIG. 1B is an illustration of a conventional processing approach used to reduce DIBL illustrating a source side boron implant (SSBI).
- SSBI source side boron implant
- FIG. 2 is a graph showing concentrations of dopant across a channel length for 2 different channel lengths.
- FIG. 3 is a graph illustrating the voltages applied to an exemplary semiconductor device during read and program modes in accordance with an embodiment of the present invention.
- FIG. 4 is a graph illustrating the effectiveness of an exemplary semiconductor to reduce DIBL in accordance with an embodiment of the present invention.
- FIG. 5 is a flow diagram of an exemplary semiconductor manufacture process is implemented to reduce DIBL in accordance with an embodiment of the present invention.
- FIG. 6A is an illustration of an exemplary semiconductor device illustrating a gate stack in accordance with an embodiment of the present invention.
- FIG. 6B is an illustration of an exemplary semiconductor device illustrating a source side boron implant in accordance with an embodiment of the present invention.
- FIG. 6C is an illustration of an exemplary semiconductor device illustrating a source implant in accordance with an embodiment of the present invention.
- FIG. 6D is an illustration of an exemplary semiconductor device illustrating a drain side implant in accordance with an embodiment of the present invention.
- FIG. 6E is an illustration of an exemplary semiconductor device illustrating a drain side counter doping implant in accordance with an embodiment of the present invention.
- FIG. 7A is a close up view of an exemplary semiconductor device illustrating a graded concentration of a source side boron implant (SSBI) in accordance with an embodiment of the present invention.
- SSBI source side boron implant
- FIG. 7B is a graph showing an alternative view of the graded concentration of a source side boron implant in accordance with an embodiment of the present invention.
- the present invention provides a method and structure for reducing DIBL and short channel effects without significantly complicating processing.
- the method and structure provide a flash memory cell having a source and a drain.
- a source side channel implant is first provided.
- the source side channel implant is boron.
- an implant is done on the drain side to counter dope the boron implant on the drain side.
- the drain side implant is arsenic and in another embodiment, the drain side implant is phosphorus.
- the present invention is incorporated into the manufacture of a semiconductor device after a gate stack is formed and before a spacer is formed.
- FIG. 3 is a graph 30 illustrating the difference in voltage applied to a flash memory cell during read and program activity.
- the voltage applied to the drain during reading 34 is approximately 0.5 volts and the voltage applied to the drain during programming 32 is approximately 5.5 volts.
- DIBL is the lowering of a threshold barrier voltage for the conduction of current across a transistor. DIBL becomes a concern typically when higher voltages are used during programming.
- voltage is applied to all devices along a bit line. If DIBL causes the threshold voltage to drop enough, current leaks across memory cells that are not selected (no gate bias) causing deleterious effects during programming.
- the threshold voltage difference between reading and programming causes current leakage in unselected transistors.
- the difference in threshold voltage between the read bias and the program bias would be zero, but a small voltage such as 0.4 volts would be acceptable.
- FIG. 4 is a graph 40 showing the difference in gate threshold voltages between read and program in a flash memory cell.
- the graph 40 plots the log of drain current 42 against the gate voltage 41 .
- the difference in threshold voltage between read and program would be zero.
- Data plot 48 and 49 illustrate an example of an ideal situation wherein the difference in gate threshold voltage is zero.
- data plot 48 (corresponding to read) and 49 (corresponding to program) have a gate threshold voltage of 1.7 volts (the two plots overlap and appear as one data plot).
- DIBL is non-existent.
- DILB is zero is for illustrative purposes to show ideal conditions.
- the difference between the read and program threshold voltage can be substantial.
- data plot 44 corresponds to the behavior of a transistor during high voltage programming when conventional channel doping is used to prevent DIBL.
- the threshold voltage for data plot 44 (program) is approximately 1 volt, wherein the threshold voltage for data plot 48 (read) is 1.7 volts.
- the difference in threshold voltage (DIBL) between read and program is approximately 0.7 volts. With DIBL close to 0.7 volts, leakage across unselected transistors is substantial and the leakage causes deleterious effects during programming and in some cases makes programming impossible.
- DIBL can be reduced to an acceptable level.
- data plot 46 program
- data plot 56 illustrates how a transistor would behave when treated with a drain side counter doping in accordance with embodiments of the present invention.
- data plot 56 has a threshold voltage of 1.4 volts.
- DIBL gate threshold voltage
- process 500 of FIG. 5 will be described in conjunction with the structure 600 of FIGS. 6A–6E which illustrate structure 600 as it undergoes process 500 in accordance with an embodiment of the present invention.
- FIG. 5 is a flow diagram of an exemplary process 500 wherein counter doping is implanted on the drain side of a semiconductor device to reduce DIBL.
- a drain side counter-doping would be implanted after a gate stack is formed.
- Detailed processing steps of forming and cutting a gate stack are eliminated from process 500 for clarity.
- intermediate processing steps such as rapid thermal anneals (RTAs) and spacer formations are not included in process 500 for clarity. While many processing steps may be provided in-between the processing steps of the present invention, the additional steps have very little bearing on the details of process 500 of the present invention.
- Process 500 of FIG. 5 starts with step 501 to form the gate stack 604 above substrate 602 as illustrated in FIG. 6A .
- a source side boron implant (SSBI) 606 of FIG. 6B is provided using conventional processing steps used in the art.
- the SSBI is a vertical implant because physical space limitations prevent an angled implant on the source. Many times, sources are in very close in proximity to each other and combined with a relatively tall gate stack an angled implant is not feasible. Dosage of the SSBI is approximately 1.5 ⁇ 10 14 p/cm 2 (particles per square centimeter).
- the length of the SSBI 608 of FIG. 6B is exaggerated for illustrative purposes.
- a source implant 608 of FIG. 6C is provided to form the source.
- the source doping is an n-type dopant.
- a drain implant 610 of FIG. 6D is provided to form the drain.
- the drain implant is also an n-type dopant.
- a drain side counter doping 612 of FIG. 6E is provided to redude the net channel doping near the drain.
- a drain side counter-doping 612 is arsenic.
- a drain side counter-doping 612 is phosphorous.
- Dosage of the drain side counter-doping is around 1 ⁇ 10 14 p/cm 2 .
- an angled implant is done to implant underneath the gate stack as far as possible.
- an angled counter-doping implant is provided at an angle 614 of FIG. 6E within approximately 30 degrees of perpendicular to the surface of the semiconductor. If an angled implant is not feasible, a vertical implant is done and then subsequent thermal cycles are provided to drive the counter-doping across the channel length.
- Process 500 illustrates an “late” approach wherein the counter-doping is provided by an angled implant.
- an “early” approach is used wherein a vertical implant is used in conjunction with a thermal cycle to drive the counter-doping across the channel length.
- Process 500 of the present invention can be applied after forming a gate stack but before forming a spacer.
- FIG. 7A is a close up illustration of semiconductor 700 in accordance with an embodiment of the present invention.
- Semiconductor 700 comprises a gate stack 704 formed above a substrate 702 .
- a source 708 has been formed on one side and a drain 710 has been formed on the opposite side.
- a SSBI 706 has been formed on the source side and a counter doping 712 has been formed on the drain side.
- FIG. 8A illustrates a graded concentration of doping (SSBI 706 ) on the source side because of the presence of the counter-doping 712 on the drain side.
- FIG. 7B is a graph 800 illustrating the concentration of doping across the channel length in accordance with an embodiment of the present invention.
- Graph 800 plots the concentration of SSBI 802 against the channel length 804 of a semiconductor. The concentration of the SSBI is greatest on the source side 708 and then slopes across the length of the channel towards the drain 710 .
- a beneficial consequence of implanting a drain side counter-doping is that the concentration if the SSBI is graded, thus reducing DIBL to a reasonable level even when feature size is small.
- the presence of arsenic (or phosphorous) on the drain side of a transistor allows the formation of a steeper graded concentration of the net doping on the source side of the transistor.
- a non-uniform concentration of the SSBI at the source reduces DIBL without increasing the gate threshold voltage.
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Abstract
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10374041B2 (en) * | 2017-12-21 | 2019-08-06 | International Business Machines Corporation | Field effect transistor with controllable resistance |
US11018171B2 (en) * | 2017-02-03 | 2021-05-25 | Sony Semiconductor Solutions Corporation | Transistor and manufacturing method |
US12015056B2 (en) | 2023-04-25 | 2024-06-18 | International Business Machines Corporation | Field effect transistor with controllable resistance |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0535917A2 (en) * | 1991-09-30 | 1993-04-07 | STMicroelectronics, Inc. | Method for fabricating integrated circuit transistors |
US5976937A (en) * | 1997-08-28 | 1999-11-02 | Texas Instruments Incorporated | Transistor having ultrashallow source and drain junctions with reduced gate overlap and method |
-
2003
- 2003-08-06 US US10/636,336 patent/US7067381B1/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0535917A2 (en) * | 1991-09-30 | 1993-04-07 | STMicroelectronics, Inc. | Method for fabricating integrated circuit transistors |
US5976937A (en) * | 1997-08-28 | 1999-11-02 | Texas Instruments Incorporated | Transistor having ultrashallow source and drain junctions with reduced gate overlap and method |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11018171B2 (en) * | 2017-02-03 | 2021-05-25 | Sony Semiconductor Solutions Corporation | Transistor and manufacturing method |
US10374041B2 (en) * | 2017-12-21 | 2019-08-06 | International Business Machines Corporation | Field effect transistor with controllable resistance |
US10586849B2 (en) | 2017-12-21 | 2020-03-10 | International Business Machines Corporation | Field effect transistor with controllable resistance |
US11177349B2 (en) | 2017-12-21 | 2021-11-16 | International Business Machines Corporation | Field effect transistor with controllable resistance |
US11855149B2 (en) | 2017-12-21 | 2023-12-26 | International Business Machines Corporation | Field effect transistor with controllable resistance |
US12015056B2 (en) | 2023-04-25 | 2024-06-18 | International Business Machines Corporation | Field effect transistor with controllable resistance |
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