DE102005053718B8 - Floating-Gate-Speicherzelle und Verfahren zum Herstellen einer Floating-Gate-Speicherzelle - Google Patents

Floating-Gate-Speicherzelle und Verfahren zum Herstellen einer Floating-Gate-Speicherzelle Download PDF

Info

Publication number
DE102005053718B8
DE102005053718B8 DE200510053718 DE102005053718A DE102005053718B8 DE 102005053718 B8 DE102005053718 B8 DE 102005053718B8 DE 200510053718 DE200510053718 DE 200510053718 DE 102005053718 A DE102005053718 A DE 102005053718A DE 102005053718 B8 DE102005053718 B8 DE 102005053718B8
Authority
DE
Germany
Prior art keywords
memory cell
floating gate
gate memory
fabricating
floating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE200510053718
Other languages
English (en)
Other versions
DE102005053718A1 (de
DE102005053718B4 (de
Inventor
Ronald Kakoschke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE200510053718 priority Critical patent/DE102005053718B8/de
Publication of DE102005053718A1 publication Critical patent/DE102005053718A1/de
Application granted granted Critical
Publication of DE102005053718B4 publication Critical patent/DE102005053718B4/de
Publication of DE102005053718B8 publication Critical patent/DE102005053718B8/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
DE200510053718 2005-11-10 2005-11-10 Floating-Gate-Speicherzelle und Verfahren zum Herstellen einer Floating-Gate-Speicherzelle Expired - Fee Related DE102005053718B8 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE200510053718 DE102005053718B8 (de) 2005-11-10 2005-11-10 Floating-Gate-Speicherzelle und Verfahren zum Herstellen einer Floating-Gate-Speicherzelle

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE200510053718 DE102005053718B8 (de) 2005-11-10 2005-11-10 Floating-Gate-Speicherzelle und Verfahren zum Herstellen einer Floating-Gate-Speicherzelle

Publications (3)

Publication Number Publication Date
DE102005053718A1 DE102005053718A1 (de) 2007-05-24
DE102005053718B4 DE102005053718B4 (de) 2014-02-13
DE102005053718B8 true DE102005053718B8 (de) 2014-04-30

Family

ID=37989257

Family Applications (1)

Application Number Title Priority Date Filing Date
DE200510053718 Expired - Fee Related DE102005053718B8 (de) 2005-11-10 2005-11-10 Floating-Gate-Speicherzelle und Verfahren zum Herstellen einer Floating-Gate-Speicherzelle

Country Status (1)

Country Link
DE (1) DE102005053718B8 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10374041B2 (en) 2017-12-21 2019-08-06 International Business Machines Corporation Field effect transistor with controllable resistance

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121654A (en) * 1997-10-10 2000-09-19 The Research Foundation Of State University Of New York Memory device having a crested tunnel barrier
ATE524833T1 (de) * 2001-04-27 2011-09-15 Imec Isolierende sperrschicht
US6784480B2 (en) * 2002-02-12 2004-08-31 Micron Technology, Inc. Asymmetric band-gap engineered nonvolatile memory device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
B.Govoreanua, D.Bruncob, J.Van Houdt, Scaling Down the Interpoly Dielectric for Next Generation Flash Memory: Challenges and Opportunities, 1st International Conf. on Memory Technology & Design (ICMTD) Giens, France, 21-24. Mai 2005
Christian Peters, Holger Sedlak Gerd Dirscherl, Michael Bollu, Andreas Schlaffer and Stefanie Thierold, A 130nm high-density embedded EEPROM as Universal Memory for code and data storage based on a 1T FN/FN Flash cell, NVSMW 2004, 22. bis 24 Aug. 2004 monterrey
G.D.Wilk et al., High-k gate dielectrics: Current status and materials properties considerations, Applied Physics Review, Journal of Applied Physics, Vol. 89, No. 10, S. 5243-5273, Mai 2001

Also Published As

Publication number Publication date
DE102005053718A1 (de) 2007-05-24
DE102005053718B4 (de) 2014-02-13

Similar Documents

Publication Publication Date Title
DE112005002339B8 (de) Einzelzelle und Verfahren zum Herstellen einer Einzelzelle; Brennstoffzelle und Verfahren zum Herstellen einer Brennstoffzelle
DE112006004278A5 (de) Glaszusammensetzung und Verfahren zum Herstellen einer Glaszusammensetzung
DE602007002041D1 (de) Nichtflüchtige Speichervorrichtung und Verfahren zum Betreiben derselben
DE602006012204D1 (de) Wasserabsorptionsmittelzusammensetzung und herstellungsverfahren dafür
DE112006000438A5 (de) Verschleissverbesserte Kette sowie Verfahren zu deren Herstellung
DE112006002999A5 (de) Solaranlage sowie Verfahren zum Betrieb
DE602006013935D1 (de) Verfahren zum Programmieren einer Speicheranordnung dafür geeignet die Kopplungen der schwebeneden Gatter zu minimieren und eine Speicheranordnung
DE102007025088B8 (de) Anzeigegerät und Verfahren zum Herstellen desselben
DE602007013393D1 (de) Brennstoffzellenstapel und verfahren zum herstellen seiner trennplatten
DE602006009540D1 (de) L und herstellungsverfahren dafür
GB2437447B (en) Memory device having trapezoidal bitlines and method of fabricating same
ATE482152T1 (de) Verpackung und verfahren zum schliessen und öffnen einer verpackung
DE602006020117D1 (de) Nadellager und herstellungsverfahren dafür
DE602005000515D1 (de) Reissverschluss und Verfahren zum Herstellen desselben
DE602006011684D1 (de) Nichtflüchtiger Halbleiterspeicher mit drei Zuständen und dessen Betriebsverfahren
DE602006004915D1 (de) Verfahren zum Herstellen einer Wabenkörperstruktur
DE112005002165A5 (de) Planar-Sensor-Anordnung, Sensor-Array und Verfahren zum Herstellen einer Planar-Sensor-Anordnung
DE602006010414D1 (de) Haarknüpfwerkzeug und herstellungsverfahren dafür
DE502006006943D1 (de) Formaldehydarmes lignocellulosematerial und verfahren zu dessen herstellung
DE602004007852D1 (de) Magnetspeichervorrichtung und Verfahren zum Herstellen einer Magnetspeichervorrichtung
DE112006003929A5 (de) Anlage und Verfahren zum Herstellen von Betonwaren
DE602006006660D1 (de) Photostabile wundverbandsmaterialien und herstellungsverfahren dafür
TWI319613B (en) Method of forming non-volatile memory cell using sacrificial pillar spacers and non-volatile memory cell formed according to the method
DE602006018360D1 (de) Kautschukzusammensetzung für seitenwand und herstellungsverfahren dafür
DE102005053718B8 (de) Floating-Gate-Speicherzelle und Verfahren zum Herstellen einer Floating-Gate-Speicherzelle

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
R018 Grant decision by examination section/examining division
R083 Amendment of/additions to inventor(s)
R020 Patent grant now final
R082 Change of representative
R020 Patent grant now final

Effective date: 20141114

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee
R079 Amendment of ipc main class

Free format text: PREVIOUS MAIN CLASS: H01L0027115000

Ipc: H01L0027115170