JP7329601B2 - 半導体デバイス、接合構造および半導体デバイスを形成するための方法 - Google Patents
半導体デバイス、接合構造および半導体デバイスを形成するための方法 Download PDFInfo
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- JP7329601B2 JP7329601B2 JP2021530781A JP2021530781A JP7329601B2 JP 7329601 B2 JP7329601 B2 JP 7329601B2 JP 2021530781 A JP2021530781 A JP 2021530781A JP 2021530781 A JP2021530781 A JP 2021530781A JP 7329601 B2 JP7329601 B2 JP 7329601B2
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Description
Claims (19)
- 複数の第1の相互接続部を備える第1の相互接続層であって、前記第1の相互接続部のうちの少なくとも1つは少なくとも1つの第1のダミー相互接続部である、第1の相互接続層、
複数の第1のボンディングコンタクトを備える第1のボンディング層であって、前記第1の相互接続部の各々は、前記第1のボンディングコンタクトのそれぞれに接触している、第1のボンディング層、および
前記第1の相互接続部のうちの少なくとも他の1つに電気的に接続される第1のデバイス層を備える、第1の半導体構造と、
複数の第2の相互接続部を備える第2の相互接続層であって、前記第2の相互接続部のうちの少なくとも1つは少なくとも1つの第2のダミー相互接続部である、第2の相互接続層、
複数の第2のボンディングコンタクトを備える第2のボンディング層であって、前記第2の相互接続部の各々は、前記第2のボンディングコンタクトのそれぞれと接触している、第2のボンディング層、および
前記第2の相互接続部のうちの少なくとも他の1つに電気的に接続される第2のデバイス層を備える、第2の半導体構造と、
前記第1のボンディング層と前記第2のボンディング層との間のボンディング界面とを備え、
前記第1のボンディングコンタクトの各々は、前記ボンディング界面において前記第2のボンディングコンタクトのそれぞれと接触しており、
前記第1のダミー相互接続部は、前記第1のデバイス層に電気的に接続されず、
前記第2のダミー相互接続部は、前記第2のデバイス層に電気的に接続されない、半導体デバイス。 - 前記第1のボンディングコンタクトの数は前記第1の相互接続部の数と同じであり、前記第2のボンディングコンタクトの数は前記第2の相互接続部の数と同じである、請求項1に記載の半導体デバイス。
- 前記第1のダミー相互接続部の数は、前記第2のダミー相互接続部の数と同じである、請求項1または2に記載の半導体デバイス。
- 前記第1のボンディングコンタクトの各々は、同じ第1の臨界寸法を有し、前記第2のボンディングコンタクトの各々は、同じ第2の臨界寸法を有する、請求項1~3のいずれか一項に記載の半導体デバイス。
- 前記第1のボンディングコンタクトおよび前記第2のボンディングコンタクトは、前記ボンディング界面において互いに接触するダミーボンディングコンタクトの対を含み、前記ダミーボンディングコンタクトの対は、第1のダミー相互接続部および第2のダミー相互接続部のそれぞれの対を電気的に接続する、請求項1~4のいずれか一項に記載の半導体デバイス。
- 前記第1のボンディング層は、第1の誘電体をさらに備え、前記第2のボンディング層は、前記ボンディング界面において前記第1の誘電体と接触する第2の誘電体をさらに備える、請求項1~5のいずれか一項に記載の半導体デバイス。
- 前記第1のボンディングコンタクトは前記ボンディング界面に均等に配置され、前記第2のボンディングコンタクトは前記ボンディング界面に均等に配置される、請求項1~6のいずれか一項に記載の半導体デバイス。
- 前記第1のデバイス層および前記第2のデバイス層のうちの一方は、前記第1のダミー相互接続部および前記第2のダミー相互接続部に電気的に接続されないNANDメモリストリングを有し、前記第1のデバイス層および前記第2のデバイス層のうちのもう一方は、前記第1のダミー相互接続部および前記第2のダミー相互接続部に電気的に接続されない周辺デバイスを有する、請求項1~7のいずれか一項に記載の半導体デバイス。
- ボンディング界面と、
前記ボンディング界面において互いに接触している機能的ボンディングコンタクトの対であって、前記機能的ボンディングコンタクトの対は、前記ボンディング界面の両側の対向する機能的相互接続部の対にそれぞれ接触している、機能的ボンディングコンタクトの対と、
前記ボンディング界面において互いに接触しているダミーボンディングコンタクトの対であって、前記ダミーボンディングコンタクトの対は、それぞれ前記ボンディング界面の前記両側の対向するダミー相互接続部の対と接触している、ダミーボンディングコンタクトの対とを備え、
前記機能的相互接続部の対は、それぞれ前記ボンディング界面の前記両側の対向するデバイス層の対に電気的に接続され、前記ダミー相互接続部の対は、それぞれ前記デバイス層の対に電気的に接続されない、接合構造。 - 前記ボンディング界面において互いに接触する誘電体の対をさらに備える、請求項9に記載の接合構造。
- 半導体デバイスを形成するための方法であって、
第1の基板の上方に、複数の第1の相互接続部を備える第1の相互接続層を形成することであって、前記第1の相互接続部のうちの少なくとも1つは少なくとも1つの第1のダミー相互接続部である、第1の相互接続層を形成することと、
複数の第1のボンディングコンタクトを備える第1のボンディング層を、前記第1の相互接続部の各々が前記第1のボンディングコンタクトのそれぞれの1つと接触するように、前記第1の相互接続層の上方に形成することと、
第2の基板の上方に、複数の第2の相互接続部を備える第2の相互接続層を形成することであって、前記第2の相互接続部のうちの少なくとも1つは少なくとも1つの第2のダミー相互接続部である、第2の相互接続層を形成することと、
複数の第2のボンディングコンタクトを備える第2のボンディング層を、前記第2の相互接続部の各々が前記第2のボンディングコンタクトのそれぞれと接触するように、前記第2の相互接続層の上方に形成することと、
前記第1の基板および前記第2の基板を、前記第1のボンディングコンタクトの各々がボンディング界面において前記第2のボンディングコンタクトのそれぞれと接触するように、フェイスツーフェイス方式で接合することと
前記第1の相互接続部のうちの少なくとも他の1つに電気的に接続される第1のデバイス層を、前記第1の相互接続層と前記第1の基板との間に形成することと、
前記第2の相互接続部のうちの少なくとも他の1つに電気的に接続される第2のデバイス層を、前記第2の相互接続層と前記第2の基板との間に形成することとを含み、
前記第1のダミー相互接続部は前記第1のデバイス層に電気的に接続されず、前記第2のダミー相互接続部は、前記第2のデバイス層に電気的に接続されない、方法。 - 前記第1のボンディング層を形成することは、単一回のパターニングプロセスによって前記第1のボンディングコンタクトを形成することを含む、請求項11に記載の方法。
- 前記第2のボンディング層を形成することは、単一回のパターニングプロセスによって前記第2のボンディングコンタクトを形成することを含む、請求項11または12に記載の方法。
- 前記第1のボンディングコンタクトの数は前記第1の相互接続部の数と同じであり、前記第2のボンディングコンタクトの数は前記第2の相互接続部の数と同じである、請求項11~13のいずれか一項に記載の方法。
- 前記第1のボンディングコンタクトの各々は、同じ第1の臨界寸法を有し、前記第2のボンディングコンタクトの各々は、同じ第2の臨界寸法を有する、請求項11~14のいずれか一項に記載の方法。
- 前記第1のボンディング層を形成することは、前記第1のボンディング層内に第1の誘電体を形成することを含み、
前記第2のボンディング層を形成することは、前記第2のボンディング層内に第2の誘電体を形成することを含み、
前記第1の誘電体は、前記接合後に前記ボンディング界面において前記第2の誘電体と接触している、請求項11~15のいずれか一項に記載の方法。 - 前記第1のデバイス層は、NANDメモリストリングを有し、
前記第2のデバイス層は、周辺デバイスを有し、
前記第1のダミー相互接続部および前記第2のダミー相互接続部は、前記NANDメモリストリングおよび前記周辺デバイスに電気的に接続されない、請求項11~16のいずれか一項に記載の方法。 - 前記第1のデバイス層は、周辺デバイスを有し、
前記第2のデバイス層は、NANDメモリストリングを有し、
前記第1のダミー相互接続部および前記第2のダミー相互接続部は、前記NANDメモリストリングおよび前記周辺デバイスに電気的に接続されない、請求項11~16のいずれか一項に記載の方法。 - 前記接合がハイブリッド接合を含む、請求項11~18のいずれか一項に記載の方法。
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